C Data Register - I2Cdr; Table 39. I 2 C Clock Setting Example - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Table 39. I 2 C Clock Setting Example
I 2 C Clock
100 kHz (Standard Mode)
400 kHz (Fast Mode)
1 MHz (Fast Mode Plus)
I 2 C Data Register – I2CDR
This register specifies the data to be transmitted or received by the I
Offset: 0x018
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset RW 0 RW
Bits Field
[7:0] DATA
Rev. 1.10
T = T
SCL PCLK
8 MHz
68
8
N/A
30 29 28
22 21 20
14 13 12
6 5 4
0 RW 0 RW
Descriptions
I C Data Register
2
For the transmitter mode, a data byte which is transmitted to a slave device can be
assigned to these bits. The TXDE flag is cleared if the application software assigns
new data to the I2CDR register. For the receiver mode, a data byte is received bit by
bit from MSB to LSB through the I
Once the acknowledge bit is given, the data shift register value is delivered into the
I2CDR register if the RXDNE flag is equal to 0.
302 of 366
× [ (SHPG + d) + (SLPG + d) ] (where d = 6)
SHPG + SLPG value at PCLK
20 MHz 24 MHz
188 228
38 48
8 12
2 C module.
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
DATA
0 RW 0 RW 0 RW
2 C interface and stored in the data shift register.
40 MHz
388
88
28
25 24
17 16
9 8
1 0
0 RW 0
November 09, 2018