Register Descriptions; Global Clock Configuration Register - Gcfgr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Register Descriptions

Global Clock Configuration Register – GCFGR
This register specifies the clock source for the PLL/USART/Watchdog Timer/CKOUT.
Offset: 0x000
Reset value: 0x0000_0102
31
Type/Reset RO 0 RO
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset
Bits Field
[31:29] LPMOD
[15:11] CKREFPRE CK_REF Clock Prescaler Selection
[8] PLLSRC
Rev. 1.10
30 29
LPMOD
0 RO 0
22 21
14 13
CKREFPRE
0 RW 0 RW
6 5
Reserved
Descriptions
Lower Power Mode Status
000: When Chip is in running mode
001: When Chip wants to enter Sleep mode
010: When Chip wants to enter Deep Sleep mode1
011: When Chip wants to enter Deep Sleep mode2
100: When Chip wants to enter Power Down mode
Others: Reserved
Set and reset by hardware.
CK_REF = CK_PLL / (CKREFPRE + 1) / 2
00000: CK_REF = CK_PLL / 2
00001: CK_REF = CK_PLL / 4
...
11111: CK_REF = CK_PLL / 64
Set and reset by software to control the CK_REF clock prescaler setting.
PLL Clock Source Selection
0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE)
1: Internal 8 MHz RC oscillator clock is selected (HSI)
Set and reset by software to control the PLL clock source.
78 of 366
28 27 26
Reserved
20 19 18
Reserved
12 11 10
0 RW 0
4 3 2
RW
25 24
17 16
9 8
Reserved PLLSRC
RW 1
1 0
CKOUTSRC
0 RW 1 RW 0
November 09, 2018