Channel Output Configuration Register - Chocfr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Channel Output Configuration Register – CHOCFR
This register specifies the channel output mode configuration.
Offset: 0x040
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[4] CHPRE
[2:0] CHOM[2:0]
Rev. 1.10
30 29 28
22 21 20
14 13 12
6 5 4
CHPRE
RW
Descriptions
Channel Capture/Compare Register (CHCCR) Preload Enable
0: CHCCR preload function is disabled
The CHCCR register can be immediately assigned a new value when the
CHPRE bit is cleared to 0 and the updated CHCCR value is used immediately.
1: CHCCR preload function is enabled
The new CHCCR value will not be transferred to its shadow register until the
update event occurs.
Channel Output Mode Setting
These bits define the functional types of the output reference signal CHOREF.
000: No Change
001: Output 0 on compare match
010: Output 1 on compare match
011: Output toggles on compare match
100: Force inactive – CHOREF is forced to 0
101: Force active – CHOREF is forced to 1
110: PWM mode 1
- During up-counting, channel has an active level when CNTR < CHCCR or
otherwise has an inactive level.
111: PWM mode 2
- During up-counting, channel has an inactive level when CNTR < CHCCR
or otherwise has an active level.
260 of 366
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
Reserved CHOM[2:0]
0 RW 0 RW
25 24
17 16
9 8
1 0
0 RW 0
November 09, 2018