Holtek HT32F52220 User Manual page 295

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Bits Field
[16] RXDNEIE
[11] TOUTIE
[10] BUSERRIE
[9] RXNACKIE
[8] ARBLOSIE
[3] GCSIE
[2] ADRSIE
[1] STOIE
[0] STAIE
Rev. 1.10
Descriptions
Data Register Not Empty Interrupt Enable Bit in Received Mode
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Timeout Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Bus Error Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Received Not Acknowledge Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Arbitration Loss Interrupt Enable Bit in the I
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
General Call Slave Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Slave Address Match Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
STOP Condition Detected Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware. The bit is used for the I
START Condition Transmit Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware. The bit is used for the I
295 of 366
C multi-master mode
2
2 C slave mode only.
2 C master mode only.
November 09, 2018