Holtek HT46R003B Manual
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Holtek HT46R003B Manual

Cost-effective a/d 8-bit otp mcu
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Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Revision: V1.00
Date: ��ne 1�� �01�
��ne 1�� �01�

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Summary of Contents for Holtek HT46R003B

  • Page 1 Cost-Effective A/D 8-bit OTP MCU HT46R003B Revision: V1.00 Date: ��ne 1�� �01� ��ne 1�� �01�...

  • Page 2: Table Of Contents

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Table of Contents Features ......................5 CPU Feat�res ......................... 5 Peripheral Feat�res ......................... 5 General Description ..................6 Block Diagram ....................6 Pin Assignment ....................6 Pin Description ....................7 Absolute Maximum Ratings ................8 D.C.

  • Page 3: Pwm Operation

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Power Down Mode and Wake-up ..............22 Power Down Mode ........................ �� Standby C�rrent Considerations ................... �� Wake-�p ..........................�� Watchdog Timer ..................... 24 Watchdog Timer Clock So�rce ....................�� Watchdog Timer Control Registers ..................��...
  • Page 4 HT46R003B Cost-Effective A/D 8-bit OTP MCU Programming Considerations ....................50 A/D Transfer F�nction ......................50 A/D Programming Example ....................51 Interrupts ......................53 Interr�pt Register ........................53 Interr�pt Operation ........................ 5� Interr�pt Priority ........................55 External Interr�pt ........................56 Timer/Event Co�nter Interr�pt ....................56 A/D Converter Interr�pt ......................

  • Page 5: Features

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Features CPU Features • Operating voltage: f = 8MHz: 2.3V~5.5V SYS • Up to 0.5μs instruction cycle with 8MHz system clock at V =5V • Power down and wake-up functions to reduce power consumption • Two oscillators Internal high speed RC – HIRC ♦ Internal 12kHz RC – LIRC ♦ • Fully integrated internal 8MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instruction • 63 powerful instructions • 4-level subroutine nesting • Bit manipulation instruction Peripheral Features • Program Memory: 1K×14 • RAM Data Memory: 64×8...

  • Page 6: General Description

    HT46R003B Cost-Effective A/D 8-bit OTP MCU General Description The device is 8-bit high performance RISC architecture microcontroller device specifically designed for a wide range of applications. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and wake-up functions, watchdog timer, as well as low cost, enhance the versatility of the device to suit for a wide range of the I/O and A/D control application possibilities such as industrial control, consumer products and subsystem controllers, etc. Block Diagram Low Voltage Reset Program Data Driver Driver Watchdog Memory Memory 8-bit Timer RISC Core Reset Circuit Interrupt Controller Time 8-bit Converter Ports Base Timer Internal RC...

  • Page 7: Pin Description

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Pin Description Pin Name Function Description PAPU CMOS General p�rpose I/O. Register enabled p�ll-�p and wake-�p. PAWU PA0/AN0 ADPCR — Analog inp�t channel 0 PAPU CMOS General p�rpose I/O. Register enabled p�ll-�p and wake-�p.

  • Page 8: Absolute Maximum Ratings

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Absolute Maximum Ratings Supply Voltage ....................V -0.3V to V +6.0V Input Voltage .................... V -0.3V to V +0.3V Storage Temperature .................... -50°C to 125°C Operating Temperature .................... -40°C to 85°C Note: T hese are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

  • Page 9: Characteristics

    HT46R003B Cost-Effective A/D 8-bit OTP MCU A.C. Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions System clock �.3V~5.5V — 3V/5V Ta=�5°C -�% +�% 3V/5V Ta=0°C~70°C System clock (HIRC) HIRC 3.0V~5.5V Ta=0°C~70°C 3.0V~5.5V Ta=-�0°C~85°C -1�% +1�% Timer I/P freq�ency (TMR) 3.3V~5.5V...

  • Page 10: Power-On Reset Characteristics

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Power-on Reset Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Start Voltage to Ens�re Power-on Reset — — — — Raising Rate to Ens�re Power-on Reset — — 0.035 — —...

  • Page 11: Program Co�Nter - Pc

    HT46R003B Cost-Effective A/D 8-bit OTP MCU S Y S ( S y s t e m C l o c k ) P h a s e C l o c k T 1 P h a s e C l o c k T 2...

  • Page 12: Stack

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The device stack is organized into 4 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. P r o g r a m C o u n t e r T o p o f S t a c k S t a c k L e v e l 1...

  • Page 13: Program Memory

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Program Memory The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP device offers users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. Structure The Program Memory has a capacity of 1K×14 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries information. Table data, which can be set in any location within the Program Memory, is addressed by separate table pointer register. 000H Initialisation Vector 00�H Interr�pt Vectors 010H n00H Look-�p Table...
  • Page 14 HT46R003B Cost-Effective A/D 8-bit OTP MCU P r o g r a m M e m o r y L a s t p a g e o r T B H P R e g i s t e r...

  • Page 15: Ram Data Memory

    HT46R003B Cost-Effective A/D 8-bit OTP MCU RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for the device is the address “00H”. All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both reading and writing operations. By using the “SET [m].i” and “CLR [m].i” instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. 0 0 H I A R 0 0 1 H M P 0...
  • Page 16 HT46R003B Cost-Effective A/D 8-bit OTP MCU IAR0 IAR1 TBLP TBLH WDTS STATUS INTC0 TMRC INTC1 PAPU PAWU PBPU CTRL0 CTRL1 WDTC ADPCR PWM0 ADRL ADRH ADCR ACSR EXTRESB : unused, read as 00H Special Purpose Data Memory Rev. 1.00 ��ne 1�� �01�...

  • Page 17: Special Function Registers

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timer, interrupts, etc., as well as external functions such as I/O data control. The locations of these registers within the Data Memory begin at the address of “00H”. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of “00H”. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation is using these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in...

  • Page 18: Acc�M�Lator - Acc

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however as the register is only 8-bit wide only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.
  • Page 19 HT46R003B Cost-Effective A/D 8-bit OTP MCU STATUS Register Name — — — — — — “x”: �nknown Bit 7~6 Unimplemented, read as “0” Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: by executing the “HALT” instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow...

  • Page 20: System Control Registers - Ctrl0, Ctrl1

    HT46R003B Cost-Effective A/D 8-bit OTP MCU System Control Registers – CTRL0, CTRL1 These registers are used to provide control internal functions such as the PFD function, the PWM function, external interrupt edge trigger type selection and Time Base function division ratio. CTRL0 Register Name — — PWMSEL — PWMC PFDC — — — — — — — — — — — — Bit 7~6 Unimplemented, read as "0" Bit 5 PWMSEL: PWM type selection 0: 6+2...

  • Page 21: Oscillator

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimization can be achieved in terms of speed and power saving. System Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer function, PWM function, Timer/Event counter and Time Base.

  • Page 22: Power Down Mode And Wake-Up

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Power Down Mode and Wake-up Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the HALT Mode or Sleep Mode. When the device enters this mode, the normal operating current will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels. However, as the device maintains its present internal condition, they can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCUs must have their power supply constantly maintained to keep the device in a known condition. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the “HALT” instruction in the application program. When this instruction is executed, the following will occur: • The system oscillator will stop running and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present condition. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.
  • Page 23 HT46R003B Cost-Effective A/D 8-bit OTP MCU If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Pins PA0~PA7 can be set via the PAWU register to permit a negative transition on the pin to wake-up the system. When a PA0~PA7 pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction.

  • Page 24: Watchdog Timer

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Watchdog Timer The Watchdog Timer, also known as the WDT, is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the LIRC oscillator, the system clock f and its division clock f /4, which are sourced from the HIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTS register. The LIRC internal oscillator has an approximate period frequency of 12kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with V , temperature and process variations. Watchdog Timer Control Registers WDTS Register Name — — — — — WS� —...
  • Page 25 HT46R003B Cost-Effective A/D 8-bit OTP MCU Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instruction. Note that if the Watchdog Timer function is not enabled, then any instruction related to the Watchdog Timer will result in no operation. Setting the various Watchdog Timer options are controlled via the internal registers WDTC and WDTS. Enabling the Watchdog Timer can be controlled by the WDTENn bits in the internal WDTC register in the Data Memory. The Watchdog Timer will be disabled if bits WDTEN5~WDTEN0 in the WDTC register are written with the binary value 101101B while the WDT Timer will be enabled if these bits are written with the binary value 000000B. If these bits are written with the other values except 000000B and 101101B, the MCU will be reset. The Watchdog Timer clock can emanate from three different sources, selected by the WDTCLS1~WDTCLS0 bits in the WDTC register. These sources are f /4 or LIRC. It is important to note that when the system enters the Sleep Mode the system clock is stopped, therefore if it has selected f or f /4 as the Watchdog Timer clock source, the Watchdog Timer will stop. For systems that operate in noisy environments, it’s recommended to use the LIRC as the clock source. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register,...

  • Page 26: Reset And Initialization

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Reset and Initialization A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to deal with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being set. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both...
  • Page 27 HT46R003B Cost-Effective A/D 8-bit OTP MCU For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimize any stray noise interference. For applications that operate within an environment where more noise is present the reset circuit shown is recommended. 0 . 0 1 m F * * V D D 1 N 4 1 4 8 * 1 0 k W ~ 1 0 0 k W R E S / P A 7 3 0 0 W * 0 .
  • Page 28 HT46R003B Cost-Effective A/D 8-bit OTP MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. This voltage is fixed at 2.1V (V ). If the supply voltage of the device drops to within a range of 0.9V~V such as might occur when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~V must exist for greater than the value t specified in the A.C. characteristics. If the low voltage state does not exceed t , the LVR will ignore it and will not perform a reset function. Note that the LVR function will automatically be disabled when the MCU enters the Power Down Mode. L V R R S T D + S S T I n t e r n a l R e s e t...
  • Page 29 HT46R003B Cost-Effective A/D 8-bit OTP MCU The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Co�nter Reset to zero Interr�pts All interr�pts will be disabled Clear after reset� WDT begins co�nting Timer/Event Co�nter Timer Co�nter will be t�rned off Precaler The Timer Co�nter Prescaler will be cleared Inp�t/O�tp�t Ports...

  • Page 30: Input/Output Ports

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. Most pins can have either an input or output designation under user program control. Additionally, as there are pull-high resistors and wake-up software configurations, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA and PB. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Register Name PA� PA� PAC7 PAC6 PAC5 PAC� PAC3 PAC� PAC1 PAC0 PAPU — PAPU6 PAPU5 PAPU� PAPU3 PAPU� PAPU1 PAPU0 PAWU...

  • Page 31: Port A Wake-�P

    HT46R003B Cost-Effective A/D 8-bit OTP MCU PBPU Register Name — — PBPU5 PBPU� PBPU3 PBPU� PBPU1 PBPU0 — — — — Bit 7~6 Unimplemented, read as "0" PBPU5~PBPU0: Port B bit 5~bit 0 pull-high control Bit 5~0 0: Disable 1: Enable Port A Wake-up If the HALT instruction is executed, the device will enter the Sleep Mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the PA0~PA7 pins from high to low. After a HALT instruction forces the microcontroller into entering the Sleep Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that pins PA0~PA7 can be selected individually to have this wake-up feature using an internal register known as PAWU, located in the Data Memory. PAWU Register...

  • Page 32: Pin-Shared F�Nctions

    HT46R003B Cost-Effective A/D 8-bit OTP MCU PBC Register Name — — PBC5 PBC� PBC3 PBC� PBC1 PBC0 — — — — Bit 7~6 Unimplemented, read as "0" PBC5~PBC0: Port B bit 5~ bit 0 Input/Output control Bit 5~0 0: Output 1: Input Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by application program control. • External Interrupt Input The external interrupt pin, INT, is pin-shared with an I/O pin. To use the pin as an external interrupt input the correct bits in the INTC0 register must be programmed. The pin must also be set as an input by setting the PAC6 bit in the Port Control Register. A pull-high resistor can also be selected via the appropriate port pull-high resistor register. Note that even if the pin is set as an external interrupt input the I/O function still remains.

  • Page 33: I/O Pin Str�Ct�Res

    HT46R003B Cost-Effective A/D 8-bit OTP MCU • A/D Iutput The device has five inputs to the A/D converter. All of these analog inputs are pin-shared with I/O pins. If these pins are to be used as A/D inputs and not as I/O pins, then the corresponding PCRn bits in the A/D converter control register, ADPCR, must be properly setup. If chosen as I/O pins, then full pull-high resistor control remains, however if used as A/D inputs then any pull-high resistor control associated with these pins will be automatically disconnected. I/O Pin Structures The accompanying diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. P u l l - H i g h C o n t r o l B i t...

  • Page 34: Programming Considerations

    HT46R003B Cost-Effective A/D 8-bit OTP MCU P u l l - H i g h R e g i s t e r C o n t r o l B i t W e a k S e l e c t...

  • Page 35: Timer/Event Counter

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Timer/Event Counter The provision of timer form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The device contains from an 8-bit count-up timer. As the timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width capture device. The provision of an internal prescaler to the clock circuitry on gives added range to the timer. There are two types of registers related to the Timer/Event Counter. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and determines how the timer is to be used. The device can have the timer clock configured to come from the internal clock source. In addition, the timer clock source can also be configured to come from an external timer pin. Configuring the Timer/Event Counter Input Clock Source The Timer/Event Counter clock source can originate from various sources, an internal clock or an external pin. The internal clock source is used when the timer is in the timer mode. For the Timer/ Event Counter, this internal clock source is first divided by a prescaler, the division ratio of which is conditioned by the Timer Control Register bits TPSC2~TPSC0. The internal clock source can be derived from the system clock f or from the instruction clock f /4 or the internal low speed oscillator LIRC for Timer/Event Counter selected by the clock selection bits WDTCLS1~WDTCLS0 in the register WDTC. An external clock source is used when the Timer/Event Counter is in the event counting mode, the clock source being provided on an external timer pin TMR. Depending upon the condition of the TEG bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. P W M...

  • Page 36: Timer Register - Tmr

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Timer Register – TMR The timer register is special function register located in the Special Purpose Data Memory and is the place where the actual timer value is stored. The register is known as TMR. The value in the timer register increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH at which point the timer overflows and an internal interrupt signal is generated. The timer value will then reset with the initial preload register value and continue counting. Note that to achieve a maximum full range count of FFH, the preload register must first be cleared. It should be noted that after power-on, the preload register will be in an unknown condition. Note that if the Timer/Event Counter is in an OFF condition and data is written to its preload register, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. Timer Control Register – TMRC The flexible features of the Holtek microcontroller Timer/Event Counter enable it to operate in three different modes, the options of which are determined by the contents of their respective control register. The Timer Control Register is known as TMRC. It is the Timer Control Register together with its corresponding timer register that controls the full operation of the Timer/Event Counter. Before the timer can be used, it is essential that the Timer Control Register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. To select which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair TM1/TM0, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TON, provides the basic on/off control of the respective timer. Setting the bit to high allows the counter to run. Clearing the bit stops the counter.

  • Page 37: Timer Mode

    HT46R003B Cost-Effective A/D 8-bit OTP MCU TEG: Timer/Event Counter active edge selection Bit 3 In event counter mode (TM1~TM0 = 01) 0: Count on rising edge 1: Count on falling edge In pulse width measurement mode (TM1~TM0 = 11) 0: Start counting on falling edge, stop on the rising edge 1: Start counting on rising edge, stop on the falling edge Bit 2~0 TPSC2~ TPSC0: Timer prescalar rate selection 000: f 001: f 010: f 011: f 100: f 101: f 110: f 111: f /128 Timer Mode In this mode, the Timer/Event Counter can be utilized to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Bit7 Bit6 Control Register Operating Mode Select Bits for the Timer Mode In this mode the internal clock is used as the timer clock. The timer input clock source is f...

  • Page 38: Event Co�Nter Mode

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer TMR pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, TM1/TM0, in the Timer Control Register must be set to the correct value as shown. Bit7 Bit6 Control Register Operating Mode Select Bits for the Timer Mode In this mode, the external timer TMR pin, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been set, the enable bit TON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit, TEG, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the TEG is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register. It is reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode. The second is to ensure that the port control register configures the pin as an input. It should be noted that in the event counting mode, even if the microcontroller is in the Sleep Mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input TMR pin. As a result when the timer overflows it will generate a timer interrupt and corresponding...

  • Page 39: Prescaler

    HT46R003B Cost-Effective A/D 8-bit OTP MCU If the Active Edge Select bit TEG which is bit 3 of the Timer Control Register is low, once a high to low transition has been received on the external timer pin, the Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. It is important to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. The residual value in the Timer/Event Counter, which can now be read by the program, therefore represents the length of the pulse received on the TMR pin. As the enable bit has now been reset, any further transitions on the external timer pin will be ignored. The timer cannot begin further pulse width capture until the enable bit is set high again by the program. In this way, single shot pulse measurements can be easily made. It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/ Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, it is reset to zero. As the TMR pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width capture pin, two things have to be implemented. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the pulse width capture mode, the second is to ensure that the port control register configure the pin as an input. E x t e r n a l T M R...

  • Page 40: Pfd F�Nction

    HT46R003B Cost-Effective A/D 8-bit OTP MCU PFD Function The Programmable Frequency Divider provides a means of producing a variable frequency output suitable for application, such as some interfaces requiring a precise frequency generator. The Timer/Event Counter overflow signal is the clock source for the PFD function, which is controlled by PFDC bit in CTRL0. For this device the clock source can come from Timer/Event Counter. The output frequency is controlled by loading the required values into the timer prescaler and timer registers to give the required division ratio. The counter will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing both the PFD outputs to change state. Then the counter will be automatically reloaded with the preload register value and continue counting-up. If the CTRL0 register has selected the PFD function, then for PFD output to operate, it is essential for the Port B control register PBC to set the PFD pins as outputs. PB5 must be set high to activate the PFD. The output data bits can be used as the on/off control bit for the PFD outputs. Note that the PFD outputs will all be low if the output data bit is cleared to zero. T i m e r O v e r f l o w...

  • Page 41: Timer Program Example

    HT46R003B Cost-Effective A/D 8-bit OTP MCU When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the Timer/Event Counter interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event Counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the “HALT” instruction to enter the Sleep Mode.

  • Page 42: Time Base

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Time Base The device includes a Time Base function which is used to generate a regular time interval signal. The Time Base time interval magnitude is determined using an internal 13 stage counter sets the division ratio of theclock source. This division ratio is controlled by both the TBSEL0 and TBSEL1 bits in the CTRL1 register. The clock source is selected using the WDTCLS1~WDTCLS0 bits in the WDTC register. When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that as the Time Base clock source is the same as the Timer/Event Counter clock source, care should be taken when programming. Pulse Width Modulator The device includes one 8-bit PWM function. Useful for the applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. PWM Operation The register, known as PWM and located in the Data Memory is assigned to each Pulse Width Modulator channel. It is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. To increase the PWM modulation frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode respectively. The required mode and the on/off control for...
  • Page 43 HT46R003B Cost-Effective A/D 8-bit OTP MCU Parameter AC (0~3) DC (Duty Cycle) i<AC (DC+1)/6� Mod�lation cycle i (i=0~3) i>AC DC/6� 6+2 Mode Modulation Cycle Values The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value. S Y S [ P W M ] = 1 0 0...

  • Page 44: Pwm O�Tp�T Control

    HT46R003B Cost-Effective A/D 8-bit OTP MCU S Y S [ P W M ] = 1 0 0 P W M 5 0 / 1 2 8 5 0 / 1 2 8 5 0 / 1 2 8 [ P W M ] = 1 0 1...

  • Page 45: Analog To Digital Converter

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains a 5-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. S Y S ¸...

  • Page 46: A/D Converter Control Registers - Adcr, Acsr, Adpcr

    HT46R003B Cost-Effective A/D 8-bit OTP MCU A/D Converter Control Registers – ADCR, ACSR, ADPCR To control the function and operation of the A/D converter, two control registers known as ADCR, ACSR and ADPCR are provided. These 8-bit registers define functions such as the on/off function, the selection of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS2~ACS0 bits in the ADCR register define the channel number. As the device contains only one actual analog to digital converter circuit, each of the individual 5 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. The PCR4~PCR0 bits contained in the ADPCR register which determine which pins on PA5, PA3~PA0 are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If the PCRn bit has a value of 1, then the corresponding pin, namely one of the AN0~AN3 analog inputs, will be set as analog inputs. Note that if the PCRn bit is set to zero, then the corresponding pin on PA5, PA3~PA0 will be set as a normal I/O pin, the analog input channels will be all disabled and the A/D converter circuitry will be powered off.
  • Page 47 HT46R003B Cost-Effective A/D 8-bit OTP MCU ACSR Register Name TEST ADONB — — — ADCS� ADCS1 ADCS0 — — — — — — Bit 7 TEST: For test mode use only ADONB: A/D Converter module on/off control bit Bit 6 0: A/D Converter module is on 1: A/D Converter module is off Note: 1. It is recommended to set ADONB=1 before entering sleep for saving power. 2. ADONB=1 will power down the A/D Converter module. Bit 5~3 Unimplemented, read as “0” Bit 2~0 ADCS2~ADCS0: Select A/D Converter clock source 000: f 001: f 010: f 011: Undefined 100: f...

  • Page 48: A/D Operation

    HT46R003B Cost-Effective A/D 8-bit OTP MCU A/D Operation The START bit in the register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set to a “1” and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to “0” by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock f , is first divided by a division ratio, the value of which is determined by the ADCS2, ADCS1 and ADCS0 bits in the ACSR register. The A/D converter overall on/off control is a function of both the ADONB bit in the ACSR register and the PCR4~PCR0 bits in the ADPCR register as shown in the table. Either the ADONB bit cleared to zero or the PCR4~PCR0 bits set to a zero value will switch off the A/D converter. These are important consideration in power sensitive applications and must be taken into account if power consumption is to be minimised. As the table illustrates, execution of the HALT instruction has no effect on the A/D converter on/off control and subsequently its power consumption. PCR4~PCR0 Bits HALT Instruction ADONB Bit A/D Converter On/Off >...
  • Page 49 HT46R003B Cost-Effective A/D 8-bit OTP MCU A/D Clock Period (t ADCS2, ADCS2, ADCS2, ADCS2, ADCS2, ADCS2, ADCS2, ADCS1, ADCS1, ADCS1, ADCS1, ADCS1, ADCS1, ADCS1, ADCS0 ADCS0 ADCS0 ADCS0 ADCS0 ADCS0 ADCS0 = 000 = 001 = 010 =100 = 101...

  • Page 50: Programming Considerations

    HT46R003B Cost-Effective A/D 8-bit OTP MCU • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. P C R 4 ~ 0 0 0 0 0 B x x x x x B - P C R [ 4 : 0 ] i s n o t e q u a l t o " 0 "...

  • Page 51: A/D Programming Example

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitized value will change at a point 1.5 LSB below the V level. 1 . 5 L S B F F F H F F E H F F D H A / D C o n v e r s i o n R e s u l t 0 .
  • Page 52 HT46R003B Cost-Effective A/D 8-bit OTP MCU Example: using the interrupt method to detect the end of conversion clr ADE ; disable A/D Converter interrupt mov a,00000001B mov ACSR,a ; select f /8 as A/D clock and ADONB=0 mov a,00011111B mov ADPCR,a ; setup ADCR register to configure I/O Port as A/D inputs mov a,00000000B mov ADCR,a ; select AN0 to be connected to the A/D converter:...

  • Page 53: Interrupts

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains only one external interrupt and multiple internal interrupts. The external interrupts are controlled by the action of the external interrupt pin, while the internal interrupt is controlled by the Timer/Event Counter, the A/D converter interrupt and Timer Base interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by using registers, INTC0 and INTC1. By controlling the appropriate enable bits in the register each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag cleared to zero will disable all interrupts. Function Enable Bit Request Flag Global —...

  • Page 54: Interr�Pt Operation

    HT46R003B Cost-Effective A/D 8-bit OTP MCU INTC1 Register Name — — — — — — — — — — — — — — — — — — Bit 7~5 Unimplemented, read as "0" TBF: time base event interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3~1 Unimplemented, read as “0” TBE: time base event interrupt enable Bit 0 0: Disable 1: Enable Interrupt Operation...

  • Page 55: Interr�Pt Priority

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. When an interrupt request is generated it takes 2 or 3 instruction cycles before the program jumps to the interrupt vector. If the device is in the Sleep Mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector. Interrupt Request or Interrupt Flag Set by Instruction Main Program Enable bit set? Main Automatically Disable Interrupt Program Clear EMI & Request Flag...

  • Page 56: External Interr�Pt

    HT46R003B Cost-Effective A/D 8-bit OTP MCU In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, INTE, must first be set. An actual external interrupt will take place when the external interrupt request flag, INTF is set, a situation that will occur when an edge transition appears on the external INT line. The type of transition that will trigger an external interrupt, whether high to low, low to high or both is determined by the INTES0 and INTES1 bits, which are bits 6 and 7 respectively in the CTRL1 control register. These two bits can also disable the external interrupt function. INTES1 INTES0 Request Flag External interr�pt disable Rising edge trigger Falling edge trigger D�al edge trigger The external interrupt pin is pin-shared with the I/O pin PA6 and can only be used as an external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has been set and the edge trigger type has been selected using the CTRL1 register. The pin must also be set as an input by setting the corresponding PAC.6 bit in the port control register. When the interrupt is enabled, the stack is not full and a transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor connections on this...

  • Page 57: Time Base Interr�Pt

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Time Base Interrupt For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will take place. When the interrupt is serviced, the time base interrupt flag. TBF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the Sleep Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the Sleep Mode and its system oscillator is stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the Sleep Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program.

  • Page 58: Application Circuits

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Application Circuits 0 . 0 1 m F * * V D D P A 0 / A N 0 P A 1 / A N 1 P A 2 / A N 2...

  • Page 59: Instruction Set

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers...

  • Page 60: Logical And Rotate Operation

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...

  • Page 61: Instruction Set Summary

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A�[m] Add Data Memory to ACC Z� C� AC� OV ADDM A�[m] Add ACC to Data Memory Note Z�...
  • Page 62 HT46R003B Cost-Effective A/D 8-bit OTP MCU Mnemonic Description Cycles Flag Affected Data Move MOV A�[m] Move Data Memory to ACC None MOV [m]�A Move ACC to Data Memory Note None MOV A�x Move immediate data to ACC None Bit Operation CLR [m].i...

  • Page 63: Instruction Definition

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x...
  • Page 64 HT46R003B Cost-Effective A/D 8-bit OTP MCU CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared.
  • Page 65 HT46R003B Cost-Effective A/D 8-bit OTP MCU CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H Affected flag(s) DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1...
  • Page 66 HT46R003B Cost-Effective A/D 8-bit OTP MCU JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ← addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ← x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory.
  • Page 67 HT46R003B Cost-Effective A/D 8-bit OTP MCU RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ← Stack ACC ← x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ← Stack EMI ← 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 Affected flag(s) None RLA [m]...
  • Page 68 HT46R003B Cost-Effective A/D 8-bit OTP MCU RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None Rotate Data Memory right through Carry RRC [m] Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0...
  • Page 69 HT46R003B Cost-Effective A/D 8-bit OTP MCU SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None Skip if increment Data Memory is 0 SIZ [m] Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the...
  • Page 70 HT46R003B Cost-Effective A/D 8-bit OTP MCU SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The...
  • Page 71 HT46R003B Cost-Effective A/D 8-bit OTP MCU TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None XOR A,[m]...

  • Page 72: Package Information

    HT46R003B Cost-Effective A/D 8-bit OTP MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.00 7� ��ne 1�� �01�...

  • Page 73: 16-Pin Dip (300Mil) O�Tline Dimensions

    HT46R003B Cost-Effective A/D 8-bit OTP MCU 16-pin DIP (300mil) Outline Dimensions & & Fig 1 Dimensions in inch Symbol Min. Nom. Max. 0.780 0.7�0 0.800 0.��0 0.�50 0.�80 0.115 0.130 0.1�5 0.115 0.130 0.150 0.01� 0.018 0.0�� 0.0�5 0.060 0.070 —...
  • Page 74 HT46R003B Cost-Effective A/D 8-bit OTP MCU Fig 2 (Type 1) Dimensions in inch Symbol Min. Nom. Max. 0.7�5 0.765 0.785 0.�75 0.�85 0.��5 0.1�0 0.135 0.150 0.110 0.130 0.150 0.01� 0.018 0.0�� 0.0�5 0.050 0.060 — 0.1 BSC — 0.300 0.310...

  • Page 75: 16-Pin Nsop (150Mil) O�Tline Dimensions

    HT46R003B Cost-Effective A/D 8-bit OTP MCU 16-pin NSOP (150mil) Outline Dimensions & Dimensions in inch Symbol Min. Nom. Max. — 0.�36 BSC — — 0.15� BSC — 0.01� — 0.0�0 C’ — 0.3�0 BSC — — — 0.06� — 0.050 BSC —...
  • Page 76 However� Holtek ass�mes no responsibility arising from the �se of the specifications described. The applications mentioned herein are used solely for the p�rpose of ill�stration and Holtek makes no warranty or representation that s�ch applications will be s�itable witho�t f�rther modification� nor recommends the �se of its prod�cts for application that may present a risk to h�man life d�e to...

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