Register Map; Table 43. Spi Register Map - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Write Collision – WC
The following conditions will assert the Write Collision Flag.
▄
The FIFOEN bit in the SPIFCR register is cleared.
The write collision flag is asserted when new data is written into the SPIDR register while both
the TX buffer and the shift register are already full. Any new data written into the TX buffer will
be lost.
▄
The FIFOEN bit in the SPIFCR register is set.
The write collision flag is asserted to indicate that new data is written into the SPIDR register
while both the TX FIFO and the TX shift register are already full. Any new data written into the
TX FIFO will be lost.
Read Overrun – RO
▄
The FIFOEN bit in the SPIFCR register is cleared.
The read overrun flag is asserted to indicate that both the RX shift register and the RX buffer are
already full, if one more data is received. This will result in the newly received data not being
shifted into the SPI shift register. As a result the latest received data will be lost.
▄
The FIFOEN bit in the SPIFCR register is set.
The read overrun flag is set to indicate that the RX shift register and the RX FIFO are both full if
one more data is received. This means that the latest received data can not be shifted into the SPI
shift register. As a result the latest received data will be lost.
Slave Abort – SA
In the SPI slave mode, the slave abort flag is set to indicate that the SEL pin suddenly changed to an
inactive state during the reception of a data frame transfer. The data frame length is set by the DFL
field in the SPICR1 register.

Register Map

The following table shows the SPI registers and their reset values.

Table 43. SPI Register Map

Register
SPICR0
SPICR1
SPIIER
SPICPR
SPIDR
SPISR
SPIFCR
SPIFSR
SPIFTOCR
Rev. 1.10
Offset
0x000 SPI Control Register 0
0x004 SPI Control Register 1
0x008 SPI Interrupt Enable Register
0x00C SPI Clock Prescaler Register
0x010 SPI Data Register
0x014 SPI Status Register
0x018 SPI FIFO Control Register
0x01C SPI FIFO Status Register
0x020 SPI FIFO Time Out Counter Register
315 of 366
Description Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0003
0x0000_0000
0x0000_0000
0x0000_0000
November 09, 2018