Timer Interrupt Control Register - Dictr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Timer Interrupt Control Register – DICTR
This register contains the timer interrupt enable control bits.
Offset: 0x074
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[10] TEVIE
[8] UEVIE
[3] CH3CCIE
[2] CH2CCIE
[1] CH1CCIE
[0] CH0CCIE
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Trigger event Interrupt Enable
0: Trigger event interrupt is disabled
1: Trigger event interrupt is enabled
Update event Interrupt Enable
0: Update event interrupt is disabled
1: Update event interrupt is enabled
Channel 3 Capture/Compare Interrupt Enable
0: Channel 3 interrupt is disabled
1: Channel 3 interrupt is enabled
Channel 2 Capture/Compare Interrupt Enable
0: Channel 2 interrupt is disabled
1: Channel 2 interrupt is enabled
Channel 1 Capture/Compare Interrupt Enable
0: Channel 1 interrupt is disabled
1: Channel 1 interrupt is enabled
Channel 0 Capture/Compare Interrupt Enable
0: Channel 0 interrupt is disabled
1: Channel 0 interrupt is enabled
223 of 366
27 26
19 18
11 10
TEVIE Reserved
RW 0
3 2
CH3CCIE CH2CCIE CH1CCIE
RW 0 RW 0 RW
25 24
17 16
9 8
UEVIE
RW 0
1 0
CH0CCIE
0 RW 0
November 09, 2018