Register Descriptions; Timer Counter Configuration Register - Cntcfr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Register Descriptions

Timer Counter Configuration Register – CNTCFR
This register specifies the SCTM counter configuration.
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[9:8] CKDIV
[1] UGDIS
[0] UEVDIS
Rev. 1.10
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Clock Division
These two bits define the frequency ratio between the timer clock (f
dead-time clock (f ). The dead-time clock is also used for digital filter sampling
DTS
clock.
00: f = f
DTS CLKIN
01: f = f / 2
DTS CLKIN
10: f = f / 4
DTS CLKIN
11: Reserved
Update event interrupt generation disable control
0: Any of the following events will generate an update interrupt
- Counter overflow
- Setting the UEVG bit
- Update generation through the slave mode
1: Only counter overflow generates an update interrupt
Update event Disable control
0: Enable the update event request by one of following events:
- Counter overflow
- Setting the UEVG bit
- Update generation through the slave mode
1: Disable the update event (However the counter and the prescaler are
reinitialized if the UEVG bit is set or if a hardware restart is received from the
slave mode)
254 of 366
27 26
Reserved
19 18
Reserved
11 10
RW
3 2
UGDIS
RW
November 09, 2018
25 24
17 16
9 8
CKDIV
0 RW 0
1 0
UEVDIS
0 RW 0
) and the
CLKIN