32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
BFTM Status Register – BFTMSR
This register specifies the BFTM status.
Offset:
0x004
Reset value: 0x0000_0004
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits
Field
[0]
MIF
Rev. 1.10
30
29
28
22
21
20
14
13
12
6
5
4
Reserved
Descriptions
BFTM Compare Match Interrupt Flag
0: No compare match event occurs
1: Compare match event occurs
When the counter value, CNT, is equal to the compare register value, CMP, a
compare match event will occur and the corresponding interrupt flag, MIF will be
set. The MIF bit is cleared to 0 by writing a data "0".
240 of 366
27
26
Reserved
19
18
Reserved
11
10
Reserved
3
2
November 09, 2018
25
24
17
16
9
8
1
0
MIF
W0C
0
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