Clock Controller; Figure 65. Sctm Clock Selection Source - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Clock Controller

The following describes the Timer Module clock controller which determines the clock source of
the internal prescaler counter.
▄
Internal APB clock f
The default internal clock source is the APB clock f
the slave mode is disabled. When the slave mode selection bits SMSEL are set to 0x4, 0x5 or
0x6, the internal APB clock f
controller is enabled by setting SMSEL field in the MDCFR register to 0x7, the prescaler is
clocked by other clock sources selected by the TRSEL field in the TRCFR register and described
as follows.
▄
STIED:
The counter prescaler can count during each rising edge of the STI signal. This mode can be
selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act
as an event counter. The input event, known as STI here, can be selected by setting the TRSEL
field to an available value except the value of 0x0. When the STI signal is selected as the clock
source, the internal edge detection circuitry will generate a clock pulse during each STI signal
rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to
0x0 to select the software UEVG bit as the trigger source, then when the SMSEL field is set to
0x7, the counter will be updated instead of counting.
f
CLKIN
(Internal APB clock)
STIED
(Trigger events)

Figure 65. SCTM Clock Selection Source

Rev. 1.10
:
CLKIN
is the counter prescaler driving clock source. If the slave mode
CLKIN
PSCR
CK_PSC
CLK
PSC Prescaler
Reset
TRSEL
SMSEL
ECME
Start/Stop
244 of 366
used to drive the counter prescaler when
CLKIN
CRR
CK_CNT
CLK
CNTR
Reset
Slave Restart
Overflow
UEVG bit
mode trigger
Update Event
TM_CNT
November 09, 2018