Channel Polarity Configuration Register - Chpolr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Channel Polarity Configuration Register – CHPOLR
This register contains the channel capture input or compare output polarity control bit.
Offset: 0x054
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[0] CHP
Rev. 1.10
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
Channel Capture/Compare Polarity
- When Channel is configured as an input
0: capture event occurs on a Channel rising edge
1: capture event occurs on a Channel falling edge
- When Channel is configured as an output (CHCCS = 0x00)
0: Channel Output is active high
1: Channel Output is active low
262 of 366
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
November 09, 2018
25 24
17 16
9 8
1 0
CHP
RW 0