I 2 C Status Register - I2Csr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
I 2 C Status Register – I2CSR
This register contains the I 2 C operation status.
Offset: 0x00C
Reset value: 0x0000_0000
31
Type/Reset
23
Reserved
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[21] TXNRX
[20] MASTER
[19] BUSBUSY
[18] RXBF
Rev. 1.10
30 29 28
22 21 20
TXNRX MASTER BUSBUSY
RO 0 RO
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Transmitter / Receiver Mode
0: Receiver mode
1: Transmitter mode
Read only bit.
Master Mode
0: I 2 C is in the slave mode or idle
1: I 2 C is in the master mode
The I 2 C interface is switched as a master device on the I
register is assigned and the I
when software disables the I
condition to the I 2 C bus or the bus error is detected. This bit is set and cleared by
hardware and is a read only bit.
Bus Busy
0: I 2 C bus is idle
1: I 2 C bus is busy
The I C interface hardware starts to detect the I
2
enabled by setting the I2CEN bit to 1. It is set to 1 when the SDA or SCL signal is
detected to have a logic low state and cleared when a STOP condition is detected.
Buffer Full Flag in Receiver Mode
0: Data buffer is not full
1: Data buffer is full
This bit is set when the data register I2CDR has already stored a data byte and
meanwhile the data shift register also has been received a complete new data byte.
The RXBF bit is cleared by software reading the I2CDR register.
297 of 366
27 26
Reserved
19 18
RXBF
0 RO 0 RO
11 10
TOUTF BUSERR
WC 0 WC
3 2
GCS ADRS
RC 0 RC
2 C bus is idle. The MASTER bit is cleared by hardware
2 C bus by clearing the I2CEN bit to 0 or sends a STOP
C bus status if the interface is
2
25 24
17 16
TXDE RXDNE
0 RO 0 RO 0
9 8
RXNACK ARBLOS
0 WC 0 WC 0
1 0
STO STA
0 RC 0 RC 0
2 C bus when the I2CTAR
November 09, 2018