Register Descriptions; Power Control Status Register - Pwrsr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Register Descriptions

Power Control Status Register – PWRSR
This register indicates the power control status.
Offset: 0x100
Reset value: 0x0000_0001 (Reset only by V
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[8] WUPF
[1] PDF
[0] PORF
Rev. 1.10
domain power on reset)
DD
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
Reserved
Descriptions
External WAKEUP Pin Flag
0: The Wakeup pin is not asserted
1: The Wakeup pin is asserted
This bit is set by hardware when the WAKEUP pin asserts and is cleared by software
read. Software should read this bit to clear it after a system wake up from the power
saving mode.
Power Down Flag
0: Wakeup from abnormal V
1: Wakeup from Power-Down mode. The loss of V
This bit is set by hardware when the system has successfully entered the Power-
Down mode. This bit is cleared by software read.
Power On Reset Flag
0: V Power Domain reset does not occur
DD
1: V Power Domain reset occurs
DD
This bit is set by hardware when V
power on reset or software reset. The bit is cleared by software read. This bit must
be cleared after the system is first powered on, otherwise it will be impossible to
detect when a V Power Domain reset has been triggered. When this bit is read
DD
as 1, a read software loop must be implemented until the bit returns again to 0.
This software loop is necessary to confirm that the V
access.
63 of 366
27 26
Reserved
19 18
Reserved
11 10
3 2
shutdown (Loss of V
DD15 DD15
is under expectation.
DD15
power on reset occurs, either a hardware
DD
Power Domain is ready for
DD
25 24
17 16
9 8
WUPF
RC 0
1 0
PDF PORF
RC 0 RC 1
is unexpected)
November 09, 2018