Figure 12. Power On Reset / Power Down Reset Waveform - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Power On Reset (POR) / Power Down Reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from/down
to 2.0 V. The device remains in Power-Down mode when V
without the need for an external reset circuit. For more details the power on / power down reset
threshold voltage, refer to the electrical characteristics of the corresponding datasheet.

Figure 12. Power On Reset / Power Down Reset Waveform

Low Voltage Detector / Brown Out Detector
The Low Voltage Detector, LVD, can detect whether the supply voltage V
programmable threshold voltage V
When a low voltage on the V
will be generated and sent to the MCU core if the LVDEN and LVDIWEN bits in the LVDCSR
register are set. For more details concerning the LVD programmable threshold voltage V
to the electrical characteristics of the corresponding datasheet.
The Brown Out Detector, BOD, is used to detect if the V
than V . When the BODEN bit in the LVDCSR register is set to 1 and the V
BOD
is lower than V
reset situation and then immediately disable the internal LDO regulator when the BODRIS bit is
cleared to 0 or issue an interrupt to notify the CPU to execute a power down procedure when the
BODRIS bit is set to 1. For more details concerning the Brown Out Detector voltage V
the electrical characteristics of the corresponding datasheet.
High Speed Internal Oscillator
The High Speed Internal Oscillator, HSI, is located in the V
the Deep-Sleep mode, the HSI clock will be configured as the system clock for a certain period
by setting the PSRCEN bit to 1 This bit is located in the Global Clock Control Register, GCCR, in
the Clock Control Unit, CKCU. The system clock will not be switched back to the original clock
source used before entering the Deep-Sleep mode until the original clock source, which may be
either sourced from the PLL or HSE stabilizes. Also the system will force the HSI oscillator to be
the system clock after a wake up from Power-Down mode since a 1.5 V power on reset will occur.
Rev. 1.10
V
DD
V
POR
Hysteresis
POR Delay Time
t
RSTD
RESET
. It is selected by the LVDS bits in the LVDCSR register.
LVD
power pin is detected, the LVDF flag will be active and an interrupt
DD
then the BODF flag is active. The PWRCU will regard this as a power down
BOD
59 of 366
is below a specified threshold V
DD
V
PDR
Time
is lower than a
DD
supply voltage is equal to or lower
DD
supply voltage
DD
BOD
power domain. When exiting from
DD
November 09, 2018
,
PDR
, refer
LVD
, refer to