32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
Timer Interrupt Control Register – DICTR
This register contains the timer interrupt enable control bits.
Offset:
0x074
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits
Field
[10]
TEVIE
[8]
UEVIE
[0]
CHCCIE
Rev. 1.10
30
29
28
22
21
20
14
13
12
Reserved
6
5
4
Reserved
Descriptions
Trigger event Interrupt Enable
0: Trigger event interrupt is disabled
1: Trigger event interrupt is enabled
Update event Interrupt Enable
0: Update event interrupt is disabled
1: Update event interrupt is enabled
Channel Capture/Compare Interrupt Enable
0: Channel interrupt is disabled
1: Channel interrupt is enabled
263 of 366
27
26
Reserved
19
18
Reserved
11
10
TEVIE
Reserved
RW
0
3
2
November 09, 2018
25
24
17
16
9
8
UEVIE
RW
0
1
0
CHCCIE
RW
0
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