Features; Function Descriptions; Master Mode; Slave Mode - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Features

▄
Master or slave mode
▄
Master mode speed up to f
▄
Slave mode speed up to f
▄
Programmable data frame length up to 16 bits
▄
FIFO Depth: 8 levels
▄
MSB or LSB first shift selection
▄
Programmable slave select high or low active polarity
▄
Multi-master and multi-slave operation
▄
Master mode supports the dual output read mode of SPI NOR Flash
▄
Four error flags with individual interrupt
● Read overrun
● Write collision
● Mode fault
● Slave abort

Function Descriptions

Master Mode

Each data frame can range from 1 to 16 bits in data length. The first bit of the transmitted data can
be either an MSB or LSB determined by the FIRSTBIT bit in the SPICR1 register. The SPI module
is configured as a master or a slave by setting the MODE bit in the SPICR1 register. When the
MODE bit is set, the SPI module is configured as a master and will generate the serial clock on the
SCK pin. The data stream will transmit data in the shift register to the MOSI pin on the serial clock
edge. The SEL pin is active during the full data transmission. When the SELAP bit in the SPICR1
register is set, the SEL pin is active high during the complete data transactions. When the SELM
bit in the SPICR1 register is set, the SEL pin will be driven by the hardware automatically and the
time interval between the active SEL edge and the first edge of SCK is equal to half an SCK period.

Slave Mode

In the slave mode, the SCK pin acts as an input pin and the serial clock will be derived from the
external master device. The SEL pin also acts as an input. When the SELAP bit is cleared to 0, the
SEL signal is active low during the full data stream reception. When the SELAP bit is set to 1, the
SEL signal will be active high during the full data stream byte reception.
Note: For the slave mode, the APB clock, known as f
external SCK clock input frequency.
Rev. 1.10
/2
PCLK
/3
PCLK
PCLK
308 of 366
, must be at least 3 times faster than the
November 09, 2018