Channel Input Configuration Register - Chicfr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Channel Input Configuration Register – CHICFR
This register specifies the channel input mode configuration.
Offset: 0x020
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[19:18] CHPSC
[17:16] CHCCS
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
6 5 4
Reserved
Descriptions
Channel Capture Input Source Prescaler Setting
These bits define the effective events of the channel capture input. Note that the
prescaler is reset once the Channel Capture/Compare Enable bit, CHE, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel capture input signal is chosen for each active event
01: Channel Capture input signal is chosen for every 2 events
10: Channel Capture input signal is chosen for every 4 events
11: Channel Capture input signal is chosen for every 8 events
Channel Capture/Compare Selection.
00: Channel is configured as an output
01: Channel is configured as an input derived from the TI signal
10: Reserved
11: Channel is configured as an input which comes from the TIBED signal
Note: The CHCCS field can be accessed only when the CHE bit is cleared to 0.
258 of 366
27 26
Reserved
19 18
CHPSC
RW 0 RW 0 RW
11 10
Reserved
3 2
RW 0 RW 0 RW
25 24
17 16
CHCCS
0 RW 0
9 8
1 0
TIF
0 RW 0
November 09, 2018