32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
GPIO x Configuration High Register – GPxCFGHR, x = A, B
This high register specifies the alternate function of GPIO Port x. x = A, B
Offset:
0x024, 0x02C
Reset value: 0x0000_0000
31
Type/Reset
RW
0 RW
23
Type/Reset
RW
0 RW
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[31:0]
PxCFGn[3:0] Port x Pin n Alternate function selection (n = 8~15)
Rev. 1.10
30
29
28
PxCFG15
0 RW
0 RW
22
21
20
PxCFG13
0 RW
0 RW
14
13
12
PxCFG11
0 RW
0 RW
6
5
4
PxCFG9
0 RW
0 RW
Descriptions
0000: Port x pin n is selected as AF0
0001: Port x pin n is selected as AF1
.
.
1110: Port x pin n is selected as AF14
1111: Port x pin n is selected as AF15
If the pin is selected as an unavailable item which is noted as a "N/A" item in the
"Alternate Function Mapping" table in the device datasheet, this pin will be defined
as the default alternate function. Please refer to the "Alternate Function Mapping"
table in the device datasheet for the detailed mapping of the alternate function I/O
pins.
136 of 366
27
26
0 RW
0 RW
0 RW
19
18
0 RW
0 RW
0 RW
11
10
0 RW
0 RW
0 RW
3
2
0 RW
0 RW
0 RW
25
24
PxCFG14
0 RW
0
17
16
PxCFG12
0 RW
0
9
8
PxCFG10
0 RW
0
1
0
PxCFG8
0 RW
0
November 09, 2018
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