Interrupts And Status; Register Map; Table 53. Uart Register Map - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Interrupts and Status

The UART can generate interrupts when the following event occurs and corresponding interrupt
enable bits are set:
▄
Receiver line status interrupts: The interrupts are generated when the UART receiver overrun
error, parity error, framing error or break events occurs.
▄
Transmit data register empty interrupt: An interrupt is generated when the content of the transmit
data register is transferred to the transmit shift register (TSR).
▄
Transmit complete interrupt: An interrupt is generated when the transmit data register (TDR) is
empty and the content of the transmit shift register (TSR) is also completely shifted.
▄
Receive data ready interrupt: An interrupt is generated when the content of the receive shift
register RDR has been transferred to the URDR register and is ready to read.

Register Map

The following table shows the UART registers and reset values.

Table 53. UART Register Map

Register
URDR
URCR
URIER
URSIFR
URDLR
URTSTR
Rev. 1.10
Offset
0x000 UART Data Register
0x004 UART Control Register
0x00C UART Interrupt Enable Register
0x010 UART Status & Interrupt Flag Register
0x024 UART Divider Latch Register
0x028 UART Test Register
358 of 366
Description Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0180
0x0000_0010
0x0000_0000
November 09, 2018