General-Purpose Timer (Gptm); Introduction; Figure 29. Gptm Block Diagram - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
13

General-Purpose Timer (GPTM)

Introduction

The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/
Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status
registers. It can be used for a variety of purposes including general timer, input signal pulse width
measurement or output waveform generation such as single pulse generation or PWM output. The
GPTM supports an encoder interface using a quadrature decoder with two inputs.
ITI0
ITI1
Edge
Detector
ITI2
UEV1G
XOR
Input Filter
TI0
& Polarity Selection
& Edge Detection
GT_CH0
Input Filter
TI1
GT_CH1
& Polarity Selection
& Edge Detection
Input Filter
TI2
GT_CH2 & Polarity Selection
& Edge Detection
Input Filter
TI3
GT_CH3 & Polarity Selection
& Edge Detection

Figure 29. GPTM Block Diagram

Rev. 1.10
f
CLKIN
TRCED
TI0BED
TI0S0ED
TI1S1ED
TI0S1ED
Quadrature
TI1S0ED
Decoder
TI0S0
TI1S1
CK_PST
PSC
PRESCALER
TI0S0ED
CH0
TI0S1ED
PRESCALER
TI1S0ED
TI1S1ED CH1
PRESCALER
TI2S2ED
CH2
TI2S3ED
PRESCALER
TI3S2ED
CH3
TI3S3ED
PRESCALER
TRCED
175 of 366
UEV1G
TME
TEV
Colck
UEV1
STIED
Controller
CHxOREF
(x = 0 ~ 3)
CLKPULSE
CEVx
MDCFR
Register
TEV : Trigger Event
CEVx : Channel x Capture Event
MEVx : Channel x Compare Match Event
STI
BEV : Break Event
Slave
Controller
Up/Dn
UEV1 : Update Event 1
Controll
UEV2 : Update Event 2
Reload Register
Restart
(CRR)
Pause
Trigger
Up/Dn
UEV1
CK_CNT
TM_CNT
MEV0
CEV0
CH0OREF
CH0 Capture/Compare
Register (CH0CCR)
MEV1
CEV1
CH1OREF
CH1 Capture/Compare
Register (CH1CCR)
MEV2
CEV2
CH2OREF
CH2 Capture/Compare
Register (CH2CCR)
MEV3
CEV3
CH3OREF
CH3 Capture/Compare
Register (CH3CCR)
MTO
Master
Controller
To other Times
To ADC
Output
GT_CH0O
Control
Output
GT_CH1O
Control
Output
GT_CH2O
Control
Output
GT_CH3O
Control
November 09, 2018