Update Management; Figure 78. Pwm Mode Channel Output Reference Signal - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Counter Value
CRR
CHCCR
CHOM = 0x06
CHOREF
CHCCIF
CHOM = 0x07
CHOREF

Figure 78. PWM Mode Channel Output Reference Signal

Update Management

The Update event is used to update the CRR, PSCR and CHCCR values from the actual registers
to the corresponding shadow registers. An update event will occur when the counter overflows, the
software update control bit is triggered or an update event from the slave controller is generated.
The UEVDIS bit in the CNTCFR register can determine whether the update event occurs or
not. When the update event occurs, the corresponding update event interrupt will be generated
depending upon whether the update event interrupt generation function is enabled or not by
configuring the UGDIS bit in the CNTCFR register. For more detailed description, refer to the
UEVDIS and UGDIS bit definition in the CNTCFR register.
Rev. 1.10
Counter Value
CHCCR
CRR
100%
CHOREF
CHCCIF
252 of 366
Counter Value
CRR
CHCCR = 0x00
CHOREF 0%
CHCCIF
November 09, 2018