Register Descriptions; Spi Control Register 0 - Spicr0 - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Register Descriptions

SPI Control Register 0 – SPICR0
This register specifies the SEL control and the SPI enable bits.
offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
GUADTEN DUALEN
Type/Reset RW 0 RW
Bits Field
[15:12] SELHT
[11:8] GUADT
[7] GUADTEN
[6] DUALEN
Rev. 1.10
30 29 28
22 21 20
14 13 12
SELHT
0 RW 0 RW
6 5 4
Reserved SSELC
0 RW
Descriptions
Chip Select Hold Time
0x0: 1/2 SCK
0x1: 1 SCK
0x2: 3/2 SCK
0x3: 2 SCK
....
Note that SELHT is for master mode only.
Guard Time
GUADTEN=1
0x0: 1 SCK
0x1: 2 SCK
0x2: 3 SCK
...
Note that GUADT is for master mode only.
Guard Time Enable
0: Guard Time is 1/2 SCK
1: When set this bit, Guard time can be controlled by GUADT
Note that GUADTEN is for master mode only.
Dual Port Enable
0: Dual port is disabled
1: Dual port is enabled
The control bit is used to support the dual output read mode of the serial SPI NOR
Flash. When this bit is set and the MOSI signal will change the direction from output
to input and receive the serial data stream. That means the DUALEN control bit is
only for master mode.
316 of 366
27 26
Reserved
19 18
Reserved
11 10
0 RW 0 RW 0 RW
3 2
SELOEN Reserved
0 RW 0
25 24
17 16
9 8
GUADT
0 RW 0
1 0
SPIEN
RW 0
November 09, 2018