32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
Bits
Field
[11]
PBE
[10]
NSB
[9:8]
WLS
[5]
URRXEN
[4]
URTXEN
[3]
HFCEN
[2]
TRSM
[1:0]
MODE
Rev. 1.10
Descriptions
Parity Bit Enable
0: Parity bit is not generated (transmitted data) or checked (receive data) during
transfer
1: Parity bit is generated or checked during transfer
Note: When the WLS field is set to "10" to select the 9-bit data format, writing to the
PBE bit has no effect.
Number of "STOP bit"
0: One "STOP bit" is generated in the transmitted data
1: Two "STOP bit" is generated when 8- and 9-bit word length is selected
Word Length Select
00: 7 bits
01: 8 bits
10: 9 bits
11: Reserved
USART RX Enable
0: Disable
1: Enable
USART TX Enable
0: Disable
1: Enable
Hardware Flow Control Function Enable
0: Disable
1: Enable
Transfer Mode Selection
This bit is used to select the data transfer protocol.
0: LSB first
1: MSB first
USART Mode Selection.
00: Normal operation
01: IrDA
10: RS485
11: Synchronous
343 of 366
November 09, 2018
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