Usart Timing Parameter Register - Usrtpr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Bits Field
[1] OEI
[0] RXDNE
USART Timing Parameter Register – USRTPR
This register contains the USART timing parameters including the transmitter time guard parameters and the
receive FIFO time-out value together with the RX FIFO time-out function enable control.
Offset: 0x014
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
RXTOEN
Type/Reset RW 0 RW
Bits Field
[15:8] TG
[7] RXTOEN
[6:0] RXTOC
Rev. 1.10
Descriptions
Overrun Error Indicator
An overrun error will occur only after the RX FIFO is full and when the next character
has been completely received in the RX shift register. The character in the shift
register is overwritten, when an overrun event occurs. However, the data in the RX
shift register will not be transferred to the RX FIFO. The OEI bit is used to indicate
the overrun event occurrence as soon as it happens. Writing 1 to this bit clears the
flag.
RX FIFO Data Not Empty
0: RX FIFO is empty
1: RX FIFO contains at least 1 received data word
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Transmitter Time Guard
The transmitter time guard counter is driven by the baud rate clock. When the
TX FIFO transmits data, the counter will be reset and then starts to count. Only
when the counter content is equal to the TG value, are further word transmission
transactions allowed.
Receive FIFO Time-Out Counter Enable
0: Receive FIFO Time-Out Counter is disabled
1: Receive FIFO Time-Out Counter is enabled
Receive FIFO Time-Out Counter Compare Value
The RX FIFO time-out counter is driven by the baud rate clock. When the RX FIFO
receives new data, the counter will be reset and then starts to count. Once the
time-out counter content is equal to the time-out counter compare value RXTOC, a
receive FIFO time-out interrupt, RXTOI, will be generated if the RXTOIE bit in the
USRIER register is set to 1. New received data or the empty RX FIFO after being
read will clear the RX FIFO time-out counter.
348 of 366
27 26
Reserved
19 18
Reserved
11 10
TG
0 RW 0 RW 0 RW
3 2
RXTOC
0 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
November 09, 2018