Data Transfer And Acknowledge; Figure 88. I 2 C Bus Acknowledge - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Data Transfer and Acknowledge

Once the slave device address has been matched, the data can be transmitted to or received from
the slave device according to the transfer direction specified by the R/W bit. Each byte is followed
by an acknowledge bit on the 9
If the slave device returns a Not Acknowledge (NACK) signal to the master device, the master
device can generate a STOP signal to terminate the data transfer or generate a repeated START
signal to restart the transfer.
If the master device sends a Not Acknowledge (NACK) signal to the slave device, the slave device
should release the SDA line for the master device to generate a STOP signal to terminate the
transfer.
SCL from
Master
Data output
by
Transmitter
Data output
by Receiver
Figure 88. I 2 C Bus Acknowledge
Rev. 1.10
th SCL clock.
Data Frame
1 2
283 of 366
Acknowledge bit
8 9
Not acknowledge
acknowledge
November 09, 2018