Holtek HT32F52220 User Manual page 16

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Figure 81. Watchdog Timer Behavior ................................................................................................... 271
Figure 82. I 2 C Module Block Diagram ................................................................................................... 278
Figure 83. START and STOP Condition ............................................................................................... 280
Figure 84. Data Validity ......................................................................................................................... 280
Figure 85. 7-bit Addressing Mode ......................................................................................................... 281
Figure 86. 10-bit Addressing Write Transmit Mode .............................................................................. 282
Figure 87. 10-bits Addressing Read Receive Mode ............................................................................ 282
Figure 88. I 2 C Bus Acknowledge .......................................................................................................... 283
Figure 89. Clock Synchronization during Arbitration ............................................................................. 284
Figure 90. Two Master Arbitration Procedure ....................................................................................... 284
Figure 91. Master Transmitter Timing Diagram .................................................................................... 286
Figure 92. Master Receiver Timing Diagram ........................................................................................ 288
Figure 93. Slave Transmitter Timing Diagram ...................................................................................... 289
Figure 94. Slave Receiver Timing Diagram .......................................................................................... 290
Figure 95. SCL Timing Diagram ............................................................................................................ 301
Figure 96. SPI Block Diagram .............................................................................................................. 307
Figure 97. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 0 ...................................... 309
Figure 98. SPI Continuous Data Transfer Timing Diagram - CPOL = 0, CPHA = 0 ............................. 310
Figure 99. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 1 ...................................... 310
Figure 100. SPI Continuous Transfer Timing Diagram - CPOL = 0, CPHA = 1 .....................................311
Figure 101. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 0 .....................................311
Figure 102. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 0 .................................... 312
Figure 103. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 1 .................................... 312
Figure 104. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 1 .................................... 312
Figure 105. SPI Multi-Master Slave Environment ................................................................................. 314
Figure 106. USART Block Diagram ...................................................................................................... 326
Figure 107. USART Serial Data Format ............................................................................................... 328
Figure 108. USART Clock CK_USART and Data Frame Timing .......................................................... 329
Figure 109. Hardware Flow Control between 2 USARTs ...................................................................... 331
Figure 110. USART RTS Flow Control.................................................................................................. 331
Figure 111. USART CTS Flow Control .................................................................................................. 332
Figure 112. IrDA Modulation and Demodulation ................................................................................... 333
Figure 113. USART I/O and IrDA Block Diagram .................................................................................. 335
Figure 114. RS485 Interface and Waveform ......................................................................................... 336
Figure 115. USART Synchronous Transmission Example .................................................................... 338
Figure 116. 8-bit Format USART Synchronous Waveform ................................................................... 339
Figure 117. UART Block Diagram ......................................................................................................... 354
Figure 118. UART Serial Data Format .................................................................................................. 355
Figure 119. UART Clock CK_UART and Data Frame Timing ............................................................... 356
Rev. 1.10 16 of 366 November 09, 2018