Flash Operation Control Register - Opcr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Flash Operation Control Register – OPCR
This register is used for controlling the command commitment and checking the status of the FMC operations.
Offset: 0x010
Reset value: 0x0000_000C
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[4:1] OPM
Rev. 1.10
30 29 28
22 21 20
14 13 12
6 5 4
RW
Descriptions
Operation Mode
The following table shows the operation modes of the FMC. User can commit the
command which is set by the OCMR register to the FMC according to the address
alias setting in the TADR register. The contents of the TADR, WRDR, and OCMR
registers should be prepared before setting this register. After all the operations
have been finished, the OPM field will be set as 0xE by the FMC hardware.
The Idle mode can be set when all the operations have been finished for power
saving purpose. Note that the operation status should be checked before the next
operation is executed to the FMC. The contents of the TADR, WRDR, OCMR,
and OPCR registers should not be changed until the previous operation has been
finished.
OPM [3:0]
0x6 Idle (default)
0xA Commit command to main Flash
0xE All operation finished on main Flash
Others Reserved
44 of 366
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
OPM
0 RW 1 RW 1 RW
Description
25 24
17 16
9 8
1 0
Reserved
0
November 09, 2018