Usart Divider Latch Register - Usrdlr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
USART Divider Latch Register – USRDLR
The register is used to determine the USART clock divided ratio to generate the appropriate baud rate.
Offset: 0x024
Reset value: 0x0000_0010
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] BRD
Rev. 1.10
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Baud Rate Divider
The 16 bits define the USART clock divider ratio.
Baud Rate = CK_USART / BRD
Where the CK_USART clock is the clock connected to the USART module.
BRD = 16 ~ 65535 for asynchronous mode
BRD = 8 ~ 65535 for synchronous mode
352 of 366
27 26
Reserved
19 18
Reserved
11 10
BRD
0 RW 0 RW 0 RW
3 2
BRD
1 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
November 09, 2018