Flash Operation Interrupt And Status Register - Oisr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Flash Operation Interrupt and Status Register – OISR
This register indicates the FMC interrupt status which is used to check if a Flash operation has been finished or
an error occurs. The status bits, bit [4:0], are available when the corresponding bits in the OIER register are set.
Offset: 0x018
Reset value: 0x0001_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[17] PPEF
[16] RORFF
[4] OREF
[3] IOCMF
[2] OBEF
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
6 5 4
OREF
WC
Descriptions
Page Erase/Program Protected Error Flag
0: Page Erase/Program Protected Error does not occur
1: Operation error occurs due to an invalid erase/program operation applied to a
protected page
This bit is reset by hardware once a new flash operation command is committed.
Raw Operation Finished Flag
0: The last flash operation command is not finished
1: The last flash operation command is finished
The RORFF bit is directly connected to the Flash memory for debugging purpose.
Operation Error Flag
0: No Flash operation error occurred
1: The last flash operation is failed
This bit will be set when any Flash operation error occurs such as an invalid
command, program error and erase error, etc. The ORE interrupt occurs if the
OREIEN bit in the OIER register is set. Reset this bit by writing 1.
Invalid Operation Command Flag
0: No invalid flash operation command was set
1: An invalid flash operation command has been written into the OCMR register
The IOCM interrupt will occur if the IOCMIEN bit in the OIER register is set. Reset
this bit by writing 1.
Option Byte Checksum Error Flag
0: Option Byte checksum is correct
1: Option Byte checksum is incorrect
The OBE interrupt will occur if the OBEIEN bit in the OIER register is set. This bit
is cleared to 0 by software writing 1 into it. However, the Option Byte Checksum
Error Flag can not be cleared by software until the interrupt condition is cleared,
which means that the Option Byte check sum value has to be correctly modified
or the corresponding interrupt control is disabled. Otherwise, the interrupt will be
continually generated.
46 of 366
27 26
Reserved
19 18
RO
11 10
Reserved
3 2
IOCMF OBEF
0 WC 0 WC 0 WC
25 24
17 16
PPEF RORFF
0 RO 1
9 8
1 0
ITADF ORFF
0 WC 0
November 09, 2018