32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
Synchronous Master Mode
The data is transmitted in a full-duplex style in the USART Synchronous Master Mode, i.e.,
data transmission and reception both occur at the same time and only support master mode. The
USART CTS pin is the synchronous USART transmitter clock output. In this mode, no clock
pulses will be sent to the CTS pin during the start bit, parity bit and stop bit duration. The CPS bit
in the Synchronous Control Register SYNCR, can be used to determine whether data is captured
on the first or the second clock edge. The CPO bit in the SYNCR can be use to configure the clock
polarity in the USART Synchronous Mode idle state. Detailed timing information is shown in
Figure 119.
In the USART synchronous Mode, the USART CTS/SCK clock output pin is only used to transmit
the data to slave device. If the transmission data register USRDR, is written with valid data, the
USART synchronous mode will automatically transmit this data with the corresponding clock
output and the USART receiver will also receive data on the RX pin. Otherwise the receiver will
not obtain synchronous data if no data is transmitted.
Figure 115. USART Synchronous Transmission Example
Note: The USART supports the synchronous master mode only: it cannot receive or send data
related to an input clock. The USART CTS/SCK clock is always an output.
Rev. 1.10
TX
RX
USART (Master)
CTS/SCK
GPIO for Chip Select
338 of 366
Data in
Data out
Device
(Slave)
Clock
CS
November 09, 2018
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