Holtek HT32F52220 User Manual page 4

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
APB Configuration Register - APBCFGR ....................................................................................... 87
APB Clock Control Register 0 - APBCCR0 .................................................................................... 88
APB Clock Control Register 1 - APBCCR1 .................................................................................... 89
Clock Source Status Register - CKST ........................................................................................... 90
APB Peripheral Clock Selection Register 0 - APBPCSR0 ............................................................. 91
APB Peripheral Clock Selection Register 1 - APBPCSR1 ............................................................. 93
Low Power Control Register - LPCR ............................................................................................. 95
MCU Debug Control Register - MCUDBGCR ................................................................................ 96
7 Reset Control Unit (RSTCU) ................................................................................ 98
Introduction .......................................................................................................................... 98
Functional Descriptions ....................................................................................................... 99
Power On Reset ............................................................................................................................. 99
System Reset ................................................................................................................................. 99
AHB and APB Unit Reset ................................................................................................................ 99
Register Map ..................................................................................................................... 100
Register Descriptions ......................................................................................................... 100
Global Reset Status Register - GRSR ......................................................................................... 100
AHB Peripheral Reset Register - AHBPRSTR ............................................................................. 101
APB Peripheral Reset Register 0 - APBPRSTR0 ........................................................................ 102
APB Peripheral Reset Register 1 - APBPRSTR1 ........................................................................ 103
8 General Purpose I/O (GPIO) ............................................................................... 104
Introduction ........................................................................................................................ 104
Features ............................................................................................................................. 105
Functional Descriptions ..................................................................................................... 105
Default GPIO Pin Configuration .................................................................................................... 105
General Purpose I/O - GPIO ........................................................................................................ 105
GPIO Locking Mechanism ............................................................................................................ 107
Register Map ..................................................................................................................... 107
Register Descriptions ......................................................................................................... 108
Port A Data Direction Control Register - PADIRCR ..................................................................... 108
Port A Input Function Enable Control Register - PAINER ............................................................ 109
Port A Pull-Up Selection Register - PAPUR ..................................................................................110
Port A Pull-Down Selection Register - PAPDR .............................................................................111
Port A Open Drain Selection Register - PAODR ...........................................................................112
Port A Output Current Drive Selection Register - PADRVR ..........................................................113
Port A Lock Register - PALOCKR .................................................................................................114
Port A Data Input Register - PADINR ............................................................................................115
Port A Output Data Register - PADOUTR .....................................................................................116
Port A Output Set/Reset Control Register - PASRR .....................................................................117
Port A Output Reset Register - PARR ...........................................................................................118
Port B Data Direction Control Register - PBDIRCR ......................................................................119
Port B Input Function Enable Control Register - PBINER ........................................................... 120
Rev. 1.10 4 of 366 November 09, 2018