High Speed Internal Rc Oscillator - Hsi - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock
Control Register (GCCR). The HSERDY flag in the Global Clock Status Register (GCSR) will
indicate if the high-speed external crystal oscillator is stable. When switching on the HSE
oscillator, the HSE clock will still not be released until this HSERDY bit is set by the hardware. The
specific delay period is well-known as "Start-up time". As the HSE becomes stable, an interrupt
will be generated if the related interrupt enable bit, HSERDYIE, in the Global Clock Interrupt
Register (GCIR) is set. The HSE clock can then be used directly as the system clock source or be
used as the PLL input clock.
High Speed Internal RC Oscillator – HSI
The high speed internal 8 MHz RC oscillator (HSI) is the default selection of the clock source for
the CPU when the device is powered up. The HSI RC oscillator provides a clock source in a lower
cost because no external components are required. The HSI RC oscillator can be switched on or off
using the HSIEN bit in the Global Clock Control Register (GCCR). The HSIRDY flag in the Global
Clock Status Register (GCSR) will indicate if the internal RC oscillator is stable. The start-up time
of the HSI oscillator is shorter than the HSE crystal oscillator. An interrupt can be generated if the
related interrupt enable bit, HSIRDYIE, in the Global Clock Interrupt Register (GCIR) is set as the
HSI becomes stable. The HSI clock can also be used as the PLL input clock.
The frequency accuracy of the high speed internal RC oscillator, HSI, can be calibrated via
the trimming operations. However, it is still less accurate than the HSE crystal oscillator. The
considerations of the applications, environments and cost will determine the selection of the
oscillators.
The software program could configure the PSRCEN bit (Power Saving Wakeup RC Clock Enable)
to 1 to force the HSI clock to be the system clock when wake-up from the Deep-Sleep or Power-
Down mode. Subsequently, the system clock is switched back to the original clock source (HSE or
PLL) if the original clock source ready flag is asserted. This function can reduce the wakeup time
when using the HSE or PLL output clock as the system clock.
Rev. 1.10 72 of 366 November 09, 2018