Holtek HT32F52220 User Manual page 15

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Figure 40. MTO Selection ..................................................................................................................... 185
Figure 41. Capture/Compare Block Diagram ........................................................................................ 186
Figure 42. Input Capture Mode ............................................................................................................. 187
Figure 43. PWM Pulse Width Measurement Example .......................................................................... 188
Figure 44. Channel 0 and Channel 1 Input Stages ............................................................................... 189
Figure 45. Channel 2 and Channel 3 Input Stages ............................................................................... 190
Figure 46. TI0 Digital Filter Diagram with N = 2 .................................................................................... 190
Figure 47. Input Stage and Quadrature Decoder Block Diagram ......................................................... 191
Figure 48. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 192
Figure 49. Output Stage Block Diagram ............................................................................................... 193
Figure 50. Toggle Mode Channel Output Reference Signal - CHxPRE = 0 ......................................... 194
Figure 51. Toggle Mode Channel Output Reference Signal - CHxPRE = 1 ......................................... 194
Figure 52. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 195
Figure 53. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 195
Figure 54. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 196
Figure 55. Update Event Setting Diagram ............................................................................................ 197
Figure 56. Single Pulse Mode ............................................................................................................... 198
Figure 57. Immediate Active Mode Minimum Delay ............................................................................. 199
Figure 58. Asymmetric PWM Mode versus Center Align Counting Mode ............................................. 200
Figure 59. BFTM Block Diagram .......................................................................................................... 236
Figure 60. BFTM - Repetitive Mode ..................................................................................................... 237
Figure 61. BFTM - One Shot Mode ...................................................................................................... 238
Figure 62. BFTM - One Shot Mode Counter Updating ....................................................................... 238
Figure 63. SCTM Block Diagram .......................................................................................................... 242
Figure 64. Up-counting Example .......................................................................................................... 243
Figure 65. SCTM Clock Selection Source ............................................................................................ 244
Figure 66. Trigger Control Block ........................................................................................................... 245
Figure 67. Slave Controller Diagram .................................................................................................... 246
Figure 68. SCTM in Restart Mode ........................................................................................................ 246
Figure 69. SCTM in Pause Mode ......................................................................................................... 247
Figure 70. SCTM in Trigger Mode ........................................................................................................ 247
Figure 71. Capture/Compare Block Diagram ........................................................................................ 248
Figure 72. Input Capture Mode ............................................................................................................. 248
Figure 73. Channel Input Stages .......................................................................................................... 249
Figure 74. TI Digital Filter Diagram with N = 2 ...................................................................................... 249
Figure 75. Output Stage Block Diagram ............................................................................................... 250
Figure 76. Toggle Mode Channel Output Reference Signal - CHPRE = 0 ........................................... 251
Figure 77. Toggle Mode Channel Output Reference Signal - CHPRE = 1 ........................................... 251
Figure 78. PWM Mode Channel Output Reference Signal ................................................................... 252
Figure 79. Update Event Setting Diagram ............................................................................................ 253
Figure 80. Watchdog Timer Block Diagram ......................................................................................... 269
Rev. 1.10 15 of 366 November 09, 2018