Sampling Time Setting; Data Format; Analog Watchdog; Table 27. Data Format In Adcdr [15:0] - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Sampling Time Setting

The conversion channel sampling time can be programmed according to the input resistance of the
input voltage source. This sampling time must be enough for the input voltage source to charge the
internal sample and hold capacitor in the A/D converter to the input voltage level. Each conversion
channel is sampled with the same sampling time. By modifying the ADST[7:0] bits in the ADCSTR
register, the sampling time of the analog input signal can be determined.
The total conversion time (T
Where the minimum sampling time T
channel conversion latency T
Example:
With the A/D Converter clock CK_ADC = 14 MHz and a sampling time =1.5 cycles:

Data Format

The ADC conversion result can be read in the ADCDRy register and the data format is shown in
the following Table 27.

Table 27. Data format in ADCDR [15:0]

Description
Right aligned

Analog Watchdog

The A/D converter includes a watchdog function to monitor the converted data. There are two
kinds of thresholds for the watchdog monitor function, known as the watchdog upper threshold
and watchdog lower threshold, which are specified in the Watchdog Upper and Lower Threshold
Registers respectively. The watchdog monitor function is enabled by setting the watchdog upper
and lower threshold monitor function enable bits, ADWUE and ADWLE, in the watchdog control
register ADCWCR. The channel to be monitored can be specified by configuring the ADWCH
and ADWALL bits. When the converted data is less or higher than the lower or upper threshold, as
defined in the ADCLTR or ADCUTR registers respectively, the watchdog lower or upper threshold
interrupt raw flags, ADIRAWL or ADIRAWU in the ADCIRAW register, will be asserted if the
watchdog lower or upper threshold monitor function is enabled. If the lower or upper threshold
interrupt raw flag is asserted and the corresponding interrupt is enabled by setting the ADIML or
ADIMU bit in the ADCIME register, the A/D watchdog lower or upper threshold interrupt will be
generated.
Rev. 1.10
) is calculated using the following formula:
conv
T = T + T
conv Sampling
= 1.5 cycles (when ADST[7:0] = 0) and the minimum
Sampling
= 12.5 cycles.
Latency
T = 1.5 + 12.5 = 14 cycles = 1 μs
conv
ADCDR register Data Format
"0_0_0_0_d11_d10_d9_d8_d7_d6_d5_d4_d3_d2_d1_d0"
158 of 366
Latency
November 09, 2018