Apb Configuration Register - Apbcfgr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
Bits Field
[0] FMCEN
APB Configuration Register – APBCFGR
This register specifies the ADC conversion clock frequency.
Offset: 0x028
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[18:16] ADCDIV
Rev. 1.10
Descriptions
Flash Memory Controller Clock Enable
0: FMC clock is automatically disabled by hardware during Sleep mode
1: FMC clock is always enabled during Sleep mode
Set and reset by software. User can set the FMCEN bit to 0 to reduce the power
consumption if the Flash Memory is unused during the Sleep mode.
30 29 28
22 21 20
Reserved
14 13 12
6 5 4
Descriptions
ADC Clock Frequency Division Selection
000: CK_ADC = (CK_AHB / 1)
001: CK_ADC = (CK_AHB / 2)
010: CK_ADC = (CK_AHB / 4)
011: CK_ADC = (CK_AHB / 8)
100: CK_ADC = (CK_AHB / 16)
101: CK_ADC = (CK_AHB / 32)
110: CK_ADC = (CK_AHB / 64)
111: CK_ADC = (CK_AHB / 3)
Set and reset by software to control the ADC conversion clock division factor.
87 of 366
27 26
Reserved
19 18
ADCDIV
RW 0 RW
11 10
Reserved
3 2
Reserved
November 09, 2018
25 24
17 16
0 RW 0
9 8
1 0