Input Stage; Figure 73. Channel Input Stages; Figure 74. Ti Digital Filter Diagram With N = 2 - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Input Stage

The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel
prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input
signal TIFP. Then the channel polarity and the edge detection block can generate a TISED signal
for the input capture function. The effective input event number can be set by the channel input
prescaler register (CHPSC).
TI
SCTM_CH
fsampling

Figure 73. Channel Input Stages

Digital Filter
The digital filters are embedded in the channel input stage. The digital filter in the SCTM is an
N-event counter where N refers to how many valid transitions are necessary to output a filtered
signal. The N value can be 0, 2, 4, 5, 6 or 8 according to the user selection for each filter.
Digital Filter (N=2)
TI
D
CK
f
SYSTEM

Figure 74. TI Digital Filter Diagram with N = 2

Rev. 1.10
f
Edge
CLKIN
Detection
Edge
Detection
f
CLKIN
TIS
TIFN
TIFP
Filter
CHP
TIF
Q D Q D Q
CK CK
f
sampling
249 of 366
CHCCS
CH
PRESCALER
TISED
Edge
Detection
CHPSC
No Filtered
TIBED
CHPSC
CHCAP Event
J Q
Filtered
CK
K
November 09, 2018