Quadrature Decoder; Figure 47. Input Stage And Quadrature Decoder Block Diagram - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Quadrature Decoder

The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GT_
CH0 and GT_CH1 pins respectively to interact to generate the counter value. The DIR bit is
modified by hardware automatically during each input source transition. The input source can be
either TI0 only, TI1 only or both TI0 and TI1, the selection made by setting the SMSEL field to
0x01, 0x02 or 0x03. The mechanism for changing the counter direction is shown in the following
table. The Quadrature decoder can be regarded as an external clock with a directional selection.
This means that the counter counts continuously in the interval between 0 and the counter-reload
value. Therefore, users must configure the CRR register before the counter starts to count.
TI0SRC
GT_CH0
TI0XOR
GT_CH1
XOR
GT_CH2
TI0
TI0FP
Filter
fsampling
TI0F
TI1
GT_CH1
TI1FP
Filter
fsampling
TI1F

Figure 47. Input Stage and Quadrature Decoder Block Diagram

Rev. 1.10
TRCED
f
CLKIN
Edge
Detection
Edge
Detection
f
CLKIN
TI0S0
TI0FN
CH0P
TI1S0
TI0S1
CH1P
TI1S1
TI1FN
191 of 366
CH0CCS
Edge TI0S0ED
Detection
CH0PRESCALER
TI1S0ED
Edge
CH0PSC
Detection
TI0S1ED
Edge
Detection
CH1PRESCALER
Edge TI1S1ED
Detection
CH1PSC
CH1CCS
TI0S0
TI1S1
TI0S0ED
Quadrature
TI1S0ED
Decoder
TI0S1ED
TI1S1ED
SMSEL
TI0BED
CH0PSC
CH0CAP Event
CH1PSC
CH1CAP Event
November 09, 2018