Spi Fifo Control Register - Spifcr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
SPI FIFO Control Register – SPIFCR
This register contains the related SPI FIFO control including the FIFO enable control and the FIFO trigger level
selections.
Offset: 0x018
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset RW 0 RW
Bits Field
[10] FIFOEN
[7:4] RXFTLS
[3:0] TXFTLS
Rev. 1.10
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
RXFTLS
0 RW 0 RW
Descriptions
FIFO Enable
0: FIFO disable
1: FIFO enable
This bit cannot be set or reset when the SPI interface is in transmitting.
RX FIFO Trigger Level Select
0000: Trigger level is 0
0001: Trigger level is 1
...
1000: Trigger level is 8
Others: Reserved
The RXFTLS field is used to specify the RX FIFO trigger level. When the number of
data contained in the RX FIFO is equal to or greater than the trigger level defined by
the RXFTLS field, the RXBNE flag will be set.
TX FIFO Trigger Level Select
0000: Trigger level is 0
0001: Trigger level is 1
...
1000: Trigger level is 8
Others: Reserved
The TXFTLS field is used to specify the TX FIFO trigger level. When the number of
data contained in the TX FIFO is equal to or less than the trigger level defined by the
TXFTLS field, the TXBE flag will be set.
323 of 366
27 26
Reserved
19 18
Reserved
11 10
FIFOEN
RW 0
3 2
0 RW 0 RW 0 RW
25 24
17 16
9 8
Reserved
1 0
TXFTLS
0 RW 0
November 09, 2018