Low Speed Internal Rc Oscillator - Lsi; Clock Ready Flag; Table 15. Output Divider2 Value Mapping; Table 16. Feedback Divider2 Value Mapping - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Table 15. Output Divider2 Value Mapping

Output divider 2 setup bits S[1:0]
(POTD bits in the PLLCFGR register)

Table 16. Feedback Divider2 Value Mapping

Feedback divider2 setup bits B[3:0]
(PFBD bits in the PLLCFGR register)
Low Speed Internal RC Oscillator – LSI
The low speed internal RC oscillator with a frequency of about 32 kHz produces a low power clock
source for the Watchdog Timer or system clock. The LSI oscillator offers a low cost clock source
because no external component is required to make it oscillates. The LSI RC oscillator is always
enable. The LSI frequency accuracy is shown in the datasheet. The LSIRDY flag in the Global
Clock Status Register (GCSR) will indicate if the LSI clock is stable. An interrupt can be generated
if the related interrupt enable bit LSIRDYIE in the Global Clock Interrupt Register (GCIR) is set as
the LSI becomes stable.

Clock Ready Flag

The CKCU provides the corresponding clock ready flags for the HSI, HSE, PLL and LSI oscillators
to indicate whether these clocks are stable. Before using them as the system clock source or other
purpose, it is necessary to confirm the specific clock ready flag is set. Software can check the
specific clock is ready or not by polling the corresponding clock ready status bits in the GCSR
register. Additionally, the CKCU can trigger an interrupt to notify that the specific clock is ready
if the corresponding interrupt enable bit in the GCIR register is set. Software should clear the
interrupt status bit in the GCIR register in the interrupt service routine.
Rev. 1.10
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
:
:
1111
74 of 366
NO2 (Output divider 2 value)
1
2
4
8
NF2 (Feedback divider 2 value)
16
1
2
3
4
5
6
7
8
9
10
11
12
:
:
15
November 09, 2018