32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
Features
▄
16-bit auto-reload up counter
▄
16-bit programmable prescaler that allows division of the counter clock frequency by any factor
between 1 and 65536
▄
Single channel for:
●
Input Capture function
●
Compare Match Output
▄
Interrupt generation with the following events:
●
Update event
●
Trigger event
●
Input capture event
●
Output compare match event
Functional Descriptions
Counter Mode
Up-Counting
The counter counts continuously from 0 to the counter-reload value, which is defined in the
CRR register. Once the counter reaches the counter-reload value, the Timer Module generates
an overflow event and the counter restarts to count once again from 0. This action will continue
repeatedly. When the update event is generated by setting the UEVG bit in the EVGR register to 1,
the counter value will also be initialized to 0.
CK_PSC
CNT_EN
CK_CNT
CNTR
CRR
F5
CRR Shadow Register
PSCR
PSCR Shadow Register
PSC_CNT
Counter Overflow
Update Event Flag
Write a new value
Figure 64. Up-counting Example
Rev. 1.10
F2
F3
F4
F5
F5
0
0
0
Update the new value
243 of 366
0
1
36
36
1
1
0
1
0
1
0
Software clearing
2
3
1
0
1
November 09, 2018
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