I 2 C Scl Low Period Generation Register - I2Cslpgr; Figure 95. Scl Timing Diagram - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
I 2 C SCL Low Period Generation Register – I2CSLPGR
This register specifies the I 2 C SCL clock low period interval.
Offset: 0x014
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] SLPG
SCL

Figure 95. SCL Timing Diagram

Rev. 1.10
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
SCL Clock Low Period Generation
Low period duration setting SCL
bus peripheral clock (PCLK) period of I
SEQFILTER in the I 2 C Control Register (I2CCR).
If SEQFILTER=00, d=6
If SEQFILTER=01, d=8
If SEQFILTER=10 or 11, d=9
High period duration
T x (SHPG+d)
PCLK
Low period duration
T x (SLPG+d)
PCLK
301 of 366
27 26
Reserved
19 18
Reserved
11 10
SLPG
0 RW 0 RW 0 RW
3 2
SLPG
0 RW 0 RW 0 RW
= T × (SLPG + d) where T
LOW PCLK
2 C, and d value depends on the setting of the
High period duration
Low period duration
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
is the APB
PCLK
November 09, 2018