Table 162. Host-Mode Control And Status Registers (Csrs) - ST STM32F205 series Reference Manual

USB on-the-go high-speed (OTG_HS)
Table 161. Core global control and status registers (CSRs) (continued)
Acronym
OTG_HS_GRXSTSR
OTG_HS_GRXSTSP
OTG_HS_GRXFSIZ
OTG_HS_GNPTXFSIZ/
OTG_HS_TX0FSIZ
OTG_HS_GNPTXSTS
OTG_HS_GCCFG
OTG_HS_CID
OTG_HS_HPTXFSIZ
OTG_HS_DIEPTXFx
Host-mode CSR map
These registers must be programmed every time the core changes to host mode.

Table 162. Host-mode control and status registers (CSRs)

Acronym
OTG_HS_HCFG
OTG_HS_HFIR
OTG_HS_HFNUM
OTG_HS_HPTXSTS
OTG_HS_HAINT
OTG_HS_HAINTMSK
OTG_HS_HPRT
1120/1378
Address
offset
0x01C
OTG_HS Receive status debug read/OTG status read and pop registers
(OTG_HS_GRXSTSR/OTG_HS_GRXSTSP) on page 1141
0x020
0x024 OTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ) on page 1142
OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size
0x028
register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ) on page 1143
OTG_HS nonperiodic transmit FIFO/queue status register
0x02C
(OTG_HS_GNPTXSTS) on page 1143
OTG_HS general core configuration register (OTG_HS_GCCFG) on
0x038
page 1144
0x03C OTG_HS core ID register (OTG_HS_CID) on page 1145
OTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ)
0x100
on page 1145
0x104
0x108
OTG_HS device IN endpoint transmit FIFO size register
(OTG_HS_DIEPTXFx) (x = 1..7, where x is the FIFO_number) on page 1146
...
0x118
Offset
address
0x400 OTG_HS host configuration register (OTG_HS_HCFG) on page 1146
0x404 OTG_HS Host frame interval register (OTG_HS_HFIR) on page 1148
OTG_HS host frame number/frame time remaining register
0x408
(OTG_HS_HFNUM) on page 1148
OTG_HS_Host periodic transmit FIFO/queue status register
0x410
(OTG_HS_HPTXSTS) on page 1149
OTG_HS Host all channels interrupt register (OTG_HS_HAINT) on
0x414
page 1150
OTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK)
0x418
on page 1150
OTG_HS host port control and status register (OTG_HS_HPRT) on
0x440
page 1151
Register name
Register name
RM0033 Rev 8
RM0033