ST STM32F205 series Reference Manual page 1129

RM0033
Bit 23 PCCI: Indicator complement
This bit controls the PHY to invert the ExternalVbusIndicator input signal, and generate the
complement output. Please refer to the ULPI specification for more details.
0: PHY does not invert the ExternalVbusIndicator signal
1: PHY inverts ExternalVbusIndicator signal
Bit 22 TSDPS: TermSel DLine pulsing selection
This bit selects utmi_termselect to drive the data line pulse during SRP (session request
protocol).
0: Data line pulsing using utmi_txvalid (default)
1: Data line pulsing using utmi_termsel
Bit 21 ULPIEVBUSI: ULPI external V
This bit indicates to the ULPI PHY to use an external V
0: PHY uses an internal V
1: PHY uses an external V
Bit 20 ULPIEVBUSD: ULPI External V
This bit selects between internal or external supply to drive 5 V on V
0: PHY drives V
1: PHY drives V
Bit 19 ULPICSM: ULPI Clock SuspendM
This bit sets the ClockSuspendM bit in the interface control register on the ULPI PHY. This bit
applies only in the serial and carkit modes.
0: PHY powers down the internal clock during suspend
1: PHY does not power down the internal clock
Bit 18 ULPIAR: ULPI Auto-resume
This bit sets the AutoResume bit in the interface control register on the ULPI PHY.
0: PHY does not use AutoResume feature
1: PHY uses AutoResume feature
Bit 17 ULPIFSLS: ULPI FS/LS select
The application uses this bit to select the FS/LS serial interface for the ULPI PHY. This bit is
valid only when the FS serial transceiver is selected on the ULPI PHY.
0: ULPI interface
1: ULPI FS/LS serial interface
Bit 16 Reserved, must be kept at reset value.
Bit 15 PHYLPCS: PHY Low-power clock select
This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the
PHY can usually operate on a 48 MHz clock to save power.
0: 480 MHz internal PLL clock
1: 48 MHz external clock
In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on
whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates
at 48 MHz in FS and LS modes.
Bit 14 Reserved, must be kept at reset value.
Bits 13:10 TRDT: USB turnaround time
These bits allows to set the turnaround time in PHY clocks. They must be configured
according to
TRDT values allow stretching the USB response time to IN tokens in order to compensate for
longer AHB read access latency to the Data FIFO.
indicator
BUS
valid comparator
BUS
valid comparator
BUS
Drive
BUS
using internal charge pump (default)
BUS
using external supply.
BUS
Table 166: TRDT values, depending on the application AHB frequency. Higher
RM0033 Rev 8
USB on-the-go high-speed (OTG_HS)
overcurrent indicator.
BUS
, in the ULPI PHY.
BUS
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