ST STM32F205 series Reference Manual page 1026

USB on-the-go full-speed (OTG_FS)
OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
Address offset: 0x81C
Reset value: 0x0000 0000
The OTG_FS_DAINTMSK register works with the Device endpoint interrupt register to
interrupt the application when an event occurs on a device endpoint. However, the
OTG_FS_DAINT register bit corresponding to that interrupt is still set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 OEPM: OUT EP interrupt mask bits
Bits 15:0 IEPM: IN EP interrupt mask bits
OTG_FS device V
Address offset: 0x0828
Reset value:
This register specifies the V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 VBUSDT: Device V
OTG_FS device V
Address offset: 0x082C
Reset value: 0x0000 05B8
This register specifies the V
1026/1378
OEPM
One per OUT endpoint:
Bit 16 for OUT EP 0, bit 19 for OUT EP 3
0: Masked interrupt
1: Unmasked interrupt
One bit per IN endpoint:
Bit 0 for IN EP 0, bit 3 for IN EP 3
0: Masked interrupt
1: Unmasked interrupt
discharge time register (OTG_FS_DVBUSDIS)
BUS
0x0000 17D7
BUS
Reserved
discharge time
BUS
Specifies the V discharge time after V
BUS
V discharge time in PHY clocks / 1 024
BUS
Depending on your V
BUS
pulsing time register (OTG_FS_DVBUSPULSE)
BUS
BUS
discharge time after V
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
pulsing during SRP. This value equals:
BUS
load, this value may need adjusting.
pulsing time during SRP.
RM0033 Rev 8
9 8 7 6 5
IEPM
pulsing during SRP.
BUS
9 8 7 6 5
VBUSDT
RM0033
4 3 2 1 0
4 3 2 1 0