ST STM32F205 series Reference Manual page 1029

RM0033
Bit 15 USBAEP: USB active endpoint
Bits 14:2 Reserved, must be kept at reset value.
Bits 1:0 MPSIZ: Maximum packet size
OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where
x = Endpoint_number)
Address offset: 0x900 + 0x20 * x
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than
endpoint 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rs rs w w w w rw rw rw rw rw
Bit 31 EPENA: Endpoint enable
Bit 30 EPDIS: Endpoint disable
Bit 29 SODDFRM: Set odd frame
This bit is always set to 1, indicating that control endpoint 0 is always active in all
configurations and interfaces.
The application must program this field with the maximum packet size for the current logical
endpoint.
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes
TXFNUM
rw rw
The application sets this bit to start transmitting data on an endpoint.
The core clears this bit before setting any of the following interrupts on this endpoint:
– SETUP phase done
– Endpoint disabled
– Transfer completed
The application sets this bit to stop transmitting/receiving data on an endpoint, even before
the transfer for that endpoint is complete. The application must wait for the Endpoint
disabled interrupt before treating the endpoint as disabled. The core clears this bit before
setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint
enable is already set for this endpoint.
Applies to isochronous IN and OUT endpoints only.
Writing to this field sets the Even/Odd frame (EONUM) field to odd frame.
USB on-the-go full-speed (OTG_FS)
Reserved
r r rw
RM0033 Rev 8
9 8 7 6 5 4
MPSIZ
rw rw rw rw rw rw rw rw rw rw rw
3 2 1 0
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