ST STM32F205 series Reference Manual page 1110

USB on-the-go high-speed (OTG_HS)
Host channel controls
The following host channel controls are available through the host channel-x characteristics
register (HCCHARx):
•
Channel enable/disable
•
Program the HS/FS/LS speed of target USB peripheral
•
Program the address of target USB peripheral
•
Program the endpoint number of target USB peripheral
•
Program the transfer IN/OUT direction
•
Program the USB transfer type (control, bulk, interrupt, isochronous)
•
Program the maximum packet size (MPS)
•
Program the periodic transfer to be executed during odd/even frames
Host channel transfer
The host channel transfer size registers (HCTSIZx) allow the application to program the
transfer size parameters, and read the transfer status.
The programming operation must be performed before setting the channel enable bit in the
host channel characteristics register. Once the endpoint is enabled, the packet count field is
read-only as the OTG HS core updates it according to the current transfer status.
The following transfer parameters can be programmed:
•
Transfer size in bytes
• Number of packets constituting the overall transfer size
•
Initial data PID
Host channel status/interrupt
The host channel-x interrupt register (HCINTx) indicates the status of an endpoint with
respect to USB- and AHB-related events. The application must read these register when the
host channels interrupt bit in the core interrupt register (HCINT bit in OTG_HS_GINTSTS) is
set. Before the application can read these registers, it must first read the host all channels
interrupt (HCAINT) register to get the exact channel number for the host channel-x interrupt
register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt
source of each channel are also available in the OTG_HS_HCINTMSK-x register.
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