ST STM32F205 series Reference Manual page 1013

RM0033
OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)
Address offset: 0x418
Reset value: 0x0000 0000
The host all channel interrupt mask register works with the host all channel interrupt register
to interrupt the application when an event occurs on a channel. There is one interrupt mask
bit per channel, up to a maximum of 16 bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 HAINTM: Channel interrupt mask
OTG_FS Host port control and status register (OTG_FS_HPRT)
Address offset: 0x440
Reset value: 0x0000 0000
This register is available only in host mode. Currently, the OTG host supports only one port.
A single register holds USB port-related information such as USB reset, enable, suspend,
resume, connect status, and test mode for each port. It is shown in
bits in this register can trigger an interrupt to the application through the host port interrupt
bit of the core interrupt register (HPRTINT bit in OTG_FS_GINTSTS). On a Port Interrupt,
the application must read this register and clear the bit that caused the interrupt. For the
rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:17 PSPD: Port speed
Reserved
0: Masked interrupt
1: Unmasked interrupt
One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
PSPD
Indicates the speed of the device attached to this port.
01: Full speed
10: Low speed
11: Reserved
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PTCTL
r r rw rw rw rw rw
RM0033 Rev 8
USB on-the-go full-speed (OTG_FS)
9 8 7 6 5
HAINTM
Figure 357. The rc_w1
9 8 7 6 5
rc_
r r rw rs rw
w1
4 3 2 1 0
4 3 2 1 0
rc_ rc_ rc_
r r
w1 w0 w1
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