Sof Trigger; Host Sofs; Peripheral Sofs; Figure 375. Sof Trigger Output To Tim2 Itr1 Connection - ST STM32F205 series Reference Manual

USB on-the-go high-speed (OTG_HS)
30.7

SOF trigger

The OTG FS core allows to monitor, track and configure SOF framing in the host and
peripheral. It also features an SOF pulse output connectivity.
These capabilities are particularly useful to implement adaptive audio clock generation
techniques, where the audio peripheral needs to synchronize to the isochronous stream
provided by the PC, or the host needs trimming its framing rate according to the
requirements of the audio peripheral.
30.7.1

Host SOFs

In host mode the number of PHY clocks occurring between the generation of two
consecutive SOF (FS) or keep-alive (LS) tokens is programmable in the host frame interval
register (OTG_HS_HFIR), thus providing application control over the SOF framing period.
An interrupt is generated at any start of frame (SOF bit in OTG_HS_GINTSTS). The current
frame number and the time remaining until the next SOF are tracked in the host frame
number register (OTG_HS_HFNUM).
An SOF pulse signal is generated at any SOF starting token and with a width of 20 HCLK
cycles. It can be made available externally on the SOF pin using the SOFOUTEN bit in the
global control and configuration register. The SOF pulse is also internally connected to the
input trigger of timer 2 (TIM2), so that the input capture feature, the output compare feature
and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled through
ITR1_RMP bits of TIM2_OR register.
30.7.2

Peripheral SOFs

In peripheral mode, the start of frame interrupt is generated each time an SOF token is
received on the USB (SOF bit in OTG_HS_GINTSTS). The corresponding frame number
can be read from the device status register (FNSOF bit in OTG_HS_DSTS). An SOF pulse
signal with a width of 20 HCLK cycles is also generated and can be made available
externally on the SOF pin by using the SOF output enable bit in the global control and
configuration register (SOFOUTEN bit in OTG_HS_GCCFG). The SOF pulse signal is also
internally connected to the TIM2 input trigger, so that the input capture feature, the output
compare feature and the timer can be triggered by the SOF pulse (see
TIM2 connection is enabled through ITR1_RMP bits of TIM2_OR register.
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Figure 375. SOF trigger output to TIM2 ITR1 connection

OTG_HS_Core
ITR1
TIM2
RM0033 Rev 8
SOF output pulse
VBUS
DP
DM
SOF
pulse ID
RM0033
ai16092
Figure 375). The