Peripheral Endpoints - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus
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USB on-the-go high-speed (OTG_HS)
30.5.3

Peripheral endpoints

The OTG_HS core instantiates the following USB endpoints:
Control endpoint 0
This endpoint is bidirectional and handles control messages only.
It has a separate set of registers to handle IN and OUT transactions, as well as
dedicated control (OTG_HS_DIEPCTL0/OTG_HS_DOEPCTL0), transfer configuration
(OTG_HS_DIEPTSIZ0/OTG_HS_DIEPTSIZ0), and status-interrupt
(OTG_HS_DIEPINTx/)OTG_HS_DOEPINT0) registers. The bits available inside the
control and transfer size registers slightly differ from other endpoints.
5 IN endpoints
5 OUT endpoints
1104/1378
They can be configured to support the isochronous, bulk or interrupt transfer type.
They feature dedicated control (OTG_HS_DIEPCTLx), transfer configuration
(OTG_HS_DIEPTSIZx), and status-interrupt (OTG_HS_DIEPINTx) registers.
The Device IN endpoints common interrupt mask register (OTG_HS_DIEPMSK)
allows to enable/disable a single endpoint interrupt source on all of the
IN endpoints (EP0 included).
They support incomplete isochronous IN transfer interrupt (IISOIXFR bit in
OTG_HS_GINTSTS). This interrupt is asserted when there is at least one
isochronous IN endpoint for which the transfer is not completed in the current
frame. This interrupt is asserted along with the end of periodic frame interrupt
(OTG_HS_GINTSTS/EOPF).
They can be configured to support the isochronous, bulk or interrupt transfer type.
They feature dedicated control (OTG_HS_DOEPCTLx), transfer configuration
(OTG_HS_DOEPTSIZx) and status-interrupt (OTG_HS_DOEPINTx) registers.
The Device Out endpoints common interrupt mask register
(OTG_HS_DOEPMSK) allows to enable/disable a single endpoint interrupt source
on all OUT endpoints (EP0 included).
They support incomplete isochronous OUT transfer interrupt (INCOMPISOOUT
bit in OTG_HS_GINTSTS). This interrupt is asserted when there is at least one
isochronous OUT endpoint on which the transfer is not completed in the current
frame. This interrupt is asserted along with the end of periodic frame interrupt
(OTG_HS_GINTSTS/EOPF).
RM0033 Rev 8
RM0033

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