Otg_Hs Low-Power Modes; Table 160. Compatibility Of Stm32 Low Power Modes With The Otg - ST STM32F205 series Reference Manual

RM0033
The end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when
80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame
interval field in the device configuration register (PFIVL bit in OTG_HS_DCFG).
This feature can be used to determine if all of the isochronous traffic for that frame is
complete.
30.8

OTG_HS low-power modes

Table 160

Table 160. Compatibility of STM32 low power modes with the OTG

Mode
Run MCU fully active
USB suspend exit causes the device to exit Sleep mode. Peripheral
Sleep
registers content is kept.
USB suspend exit causes the device to exit Stop mode. Peripheral
Stop
registers content is kept
Powered-down. The peripheral must be reinitialized after exiting
Standby
Standby mode.
1. Within Stop mode there are different possible settings. Some restrictions may also exist, please refer to
control (PWR) to understand which (if any) restrictions apply when using OTG.
The following bits and procedures reduce power consumption.
The power consumption of the OTG PHY is controlled by three bits in the general core
configuration register:
•
PHY power down (GCCFG/PWRDWN)
This bit switches on/off the PHY full-speed transceiver module. It must be preliminarily
set to allow any USB operation.
• A-VBUS sensing enable (GCCFG/VBUSASEN)
This bit switches on/off the V
must be set when in A-device (USB host) mode and during HNP.
•
B-VBUS sensing enable (GCCFG/VBUSASEN)
This bit switches on/off the V
must be set when in B-device (USB peripheral) mode and during HNP.
Power reduction techniques are available in the USB suspended state, when the USB
session is not yet valid or the device is disconnected.
• Stop PHY clock (STPPCLK bit in OTG_HS_PCGCCTL)
–
below defines the STM32 low power modes and their compatibility with the OTG.
Description
(1)
.
When setting the stop PHY clock bit in the clock gating control register, most of the
clock domain internal to the OTG high-speed core is switched off by clock gating.
USB on-the-go high-speed (OTG_HS)
comparators associated with A-device operations. It
BUS
comparators associated with B-device operations. It
BUS
RM0033 Rev 8
USB compatibility
Required when USB not in
suspend state.
Available while USB is in
suspend state.
Available while USB is in
suspend state.
Not compatible with USB
applications.
Section 4: Power
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